SoC compatible 1 T1 C FeRAM memory array based on ferroelectric Hf0.5Zr0.5O2

SoC compatible 1 T1 C FeRAM memory array based on ferroelectric Hf0.5Zr0.5O2
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基于铁电 Hf0.5Zr0.5O2 的 SoC 兼容 1 T1 C FeRAM 存储器阵列

DOI:
10.1109/vlsitechnology18217.2020.9265063
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发表时间:
2020
期刊:
2020 IEEE Symposium on VLSI Technology
影响因子:
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通讯作者:
T. Umebayashi
T. Umebayashi
中科院分区:
--
文献类型:
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作者:
J. Okuno;Takafumi Kunihiro;Kenta Konishi;Hideki Maemura;Yusuke Shute;Fumitaka Sugaya;M. Materano;T. Ali;Kati Kuehnel;Konrad Seide;U. Schroeder;T. Mikolajick;M. Tsukamoto;T. Umebayashi

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本文通过实验展示了基于铁电\(HfO_2\)的1T1C铁电随机存取存储器(FeRAM)的基本存储阵列操作。由\(TiN/Hf_{0.5}Zr_{0.5}O_2(HZO)/TiN\)堆叠构成的金属/铁电/金属(MFM)电容器针对低于\(500^{\circ}C\)的工艺进行了优化。这些结构展现出了优异的性能,例如剩余极化\(2P_r>4|\mu C/cm^2\),耐久性\(>10^{11}\)次循环,以及在\(85^{\circ}C\)下数据保持10年。此外,MFM电容器成功集成到一个64 kbit的1T1C FeRAM阵列中,该阵列包括我们专门用于阵列操作的电路。后端制程(BEOL)布线未显示底层CMOS逻辑性能下降。编程和读取操作得到了恰当控制,在\(2.5V\)的操作电压和\(14ns\)的操作速度下实现了\(100\%\)的位功能。这项技术符合物联网应用中低功耗片上系统(SoC)的末级缓存(LLC)和嵌入式非易失性存储器(NVM)的要求。
This paper experimentally demonstrates fundamental memory array operation of a ferroelectric HfO2-based 1 T1 C FeRAM. Metal/ferroelectric/metal (MFM) capacitors consisting of a TiN/ $\mathrm{Hf}_{0.5}\mathrm{Zr}_{0.5}\mathrm{O}_{2}(\mathrm{HZO}$)/TiN stack were optimized for a sub 500°C process. Structures revealed excellent performance such as remanent polarization $2\mathrm{P}_{\mathrm{r}} > 4\vert \mu\mathrm{C}/\mathrm{cm}^{2}$, endurance> 1011 cycles, and 10 years data retention at 85°C. Furthermore, the MFM capacitors were successfully integrated into a 64 kbit 1T1C FeRAM array including our dedicated circuit for array operation. Back-end-of-line (BEOL) wiring showed no degradation of the underlying CMOS logic. Program and read operation were properly controlled resulting in 100 % bit functionality at an operation voltage of2.5 Vand operating speed at 14 ns. This technology matches requirements of last level cash (LLC) and embedded non-volatile-memory (NVM) in low power System-on-a-Chip (SoC) for IoT applications.