Capturing all branches of any one-port characteristic in piecewise-linear resistive circuits
Capturing all branches of any one-port characteristic in piecewise-linear resistive circuits
复制标题
捕获分段线性电阻电路中任何单端口特性的所有分支
DOI：
10.1109/81.481458
复制
发表时间：
1996
影响因子：
5.1
通讯作者：
A. Premoli
中科院分区：
文献类型：
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作者：
S. Pastore;A. Premoli
本文描述了一种捕捉分段线性（PWL）电阻电路中任意单端口特性的所有通用分支的算法。该算法的核心是基于所谓的多面体增强电路：它们是通过用合适的多面体元件替换每个PWL元件并将一个调节器连接到单端口来构建的。该算法的结构基于一个谱系树，其节点代表特定的多面体增广电路。通过检查这些电路的解域，可以捕获PWL单端口特性的所有分支。从数值的角度来看，对节点的调查需要执行相关的线性规划（LP）问题，每个节点一个，然而，它们的表的相似结构允许减少总体CPU时间。
An algorithm to capture all the unicursal branches of any one-port characteristic in piecewise-linear (PWL) resistive circuits is described. The heart of this algorithm is based on the so-called polyhedral augmented circuits: they are constructed by replacing each PWL element by a suitable polyhedral element and by connecting a norator to the one-port. The structure of the algorithm is based on a genealogical tree, whose nodes represent specific polyhedral augmented circuits. All branches of the PWL one-port characteristic can be captured by checking the solution domains of these circuits. From the numerical point of view, the investigation of the nodes requires the execution of related Linear Programming (LP) problems, one for each node, However, the similar structure of their tableaux allows the reduction of the overall CPU time.
DOI：
--
发表时间：
2004
期刊：
Proceedings of IEEE 2004 International Conference on Communications, Circuits and Systems II
影响因子：
--
作者：
Kiyotaka Yamamura;Akinori Machida;Kiyotaka Yamamura
通讯作者：
Kiyotaka Yamamura