SPR: an architecture-adaptive CGRA mapping tool
SPR: an architecture-adaptive CGRA mapping tool
复制标题
DOI：
10.1145/1508128.1508158
复制
发表时间：
2009-02
期刊：
影响因子：
3.9
通讯作者：
Stephen Friedman;Allan Carroll;B. V. Essen;Benjamin Ylvisaker;C. Ebeling;S. Hauck
中科院分区：
文献类型：
--
作者：
Stephen Friedman;Allan Carroll;B. V. Essen;Benjamin Ylvisaker;C. Ebeling;S. Hauck
在本文中，我们提出了 SPR，一种新的架构自适应映射工具，可与粗粒度可重构架构 (CGRA) 一起使用。它将 VLIW 风格的调度器和 FPGA 风格的布局和流水线路由算法与用于将算法集成和适应 CGRA 的新颖机制相结合。我们引入了一种延迟填充技术，该技术提供从布局器到调度器的反馈，以满足具有可配置互连的固定频率设备的限制。在布局过程中使用新的动态聚类方法，我们将映射设计的吞吐量提高了 1.3 倍。最后，我们引入了 PathFinder 算法的增强功能，用于混合动态多路复用和静态可配置互连的目标架构。增强型算法能够以时分复用方式成功共享静态配置互连，与非共享静态互连相比，平均通道宽度减少了 0.5 倍。
In this paper we present SPR, a new architecture-adaptive mapping tool for use with Coarse-Grained Reconfigurable Architectures (CGRAs). It combines a VLIW style scheduler and FPGA style placement and pipelined routing algorithms with novel mechanisms for integrating and adapting the algorithms to CGRAs. We introduce a latency padding technique that provides feedback from the placer to the scheduler to meet the constraints of a fixed frequency device with configurable interconnect. Using a new dynamic clustering method during placement, we achieved a 1.3x improvement in throughput of mapped designs. Finally, we introduce an enhancement to the PathFinder algorithm for targeting architectures with a mix of dynamically multiplexed and statically configurable interconnects. The enhanced algorithm is able to successfully share statically configured interconnect in a time-multiplexed way, achieving an average channel width reduction of .5x compared to non-shared static interconnect.