6-bit CMOS Digital Attenuators With Low Phase Variations for $X$-Band Phased-Array Systems
6-bit CMOS Digital Attenuators With Low Phase Variations for $X$-Band Phased-Array Systems
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DOI：
10.1109/tmtt.2010.2049691
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发表时间：
2010-05
影响因子：
4.3
通讯作者：
B. Ku;Songcheol Hong
中科院分区：
文献类型：
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作者：
B. Ku;Songcheol Hong
本文介绍了一种低相位变化的6位CMOS数字步进衰减器。为了减轻传统开关Pi/T衰减器的插入相位变化，所提出的衰减器采用补偿电路。这包括用于相位/幅度校正的低通滤波器。分析比较了两种具有电感和电容校正电路的π型衰减器。这两种衰减器均采用0.18 μ mCMOS工艺制作。衰减器的最大衰减范围为31.5 dB，步长为0.5 dB（64个状态）。在8-12 GHz频率范围内，采用电感和电容校正结构的衰减器的均方根幅度误差分别小于0.3和0.4 dB，均方根相位误差分别小于3.5°和2°。插入损耗分别为8.7和10.5 dB，在10 GHz。10 GHz时，输入1 dB压缩点为15和13 dBm，芯片总尺寸（不包括焊盘）分别为1.25 × 0.4 mm 2和0.67 × 0.5 mm 2。
This paper presents 6-bit CMOS digital step attenuators with low phase variations. To mitigate the insertion phase variation of conventional switched Pi/T attenuators, the proposed attenuators employ a compensation circuit. This includes a low-pass filter for phase/amplitude correction. Analysis and comparison of two types of Pi-attenuators with the inductive and capacitive correction circuits are described. The two types of attenuators are fabricated using a 0.18-μm CMOS process. The attenuators have a maximum attenuation range of 31.5 dB with 0.5-dB steps (64 states). The attenuators with the inductive and capacitive correction structures, respectively, exhibit root mean square (rms) amplitude errors of less than 0.3 and 0.4 dB, and rms phase errors of less than 3.5° and 2° at 8-12 GHz. The insertion losses are 8.7 and 10.5 dB at 10 GHz, respectively. The input 1-dB compression points are 15 and 13 dBm at 10 GHz, and the total chip sizes, excluding pads, are 1.25 × 0.4 mm2 and 0.67 × 0.5 mm2.