AXI HyperConnect: A Predictable, Hypervisor-level Interconnect for Hardware Accelerators in FPGA SoC
AXI HyperConnect: A Predictable, Hypervisor-level Interconnect for Hardware Accelerators in FPGA SoC
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AXI HyperConnect：用于 FPGA SoC 中硬件加速器的可预测的管理程序级互连
DOI：
10.1109/dac18072.2020.9218652
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发表时间：
2020
期刊：
影响因子：
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通讯作者：
G. Buttazzo
中科院分区：
文献类型：
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作者：
Francesco Restuccia;Alessandro Biondi;Mauro Marinoni;Giorgiomaria Cicero;G. Buttazzo
基于FPGA的芯片系统（SOC）是强大的计算平台，用于实现需要多处理和硬件加速的混合批判性系统。通过操纵组织技术虚拟化是一种有效的技术，可以允许在同一平台上隔离具有不同临界级别的多个执行域。在基于FPGA的SOC上实施此类技术提出了新的挑战：其中之一是隔离属于不同域但共享常见资源（例如内存总线）的硬件加速器。本文提出了Axi HyperConnect，这是一种管理程序级硬件组件，允许将硬件加速器互连到同一总线，同时确保隔离和可预测性功能。 AXI HyperConnect已通过Xilinx在现代FPGA-SOC上实施，并使用现实世界加速器进行了测试，其中包括用于深神经网络推断。
FPGA-based system-on-chips (SoC) are powerful computing platforms to implement mixed-criticality systems that require both multiprocessing and hardware acceleration. Virtualization via hypervisor technologies is, de-facto, an effective technique to allow the co-existence of multiple execution domains with different criticality levels in isolation upon the same platform. Implementing such technologies on FPGA-based SoC poses new challenges: one of such is the isolation of hardware accelerators deployed on the FPGA fabric that belong to different domains but share common resources such as a memory bus. This paper proposes AXI HyperConnect, a hypervisor-level hardware component that allows interconnecting hardware accelerators to the same bus while ensuring isolation and predictability features. AXI HyperConnect has been implemented on modern FPGA-SoC by Xilinx and tested with real-world accelerators, including one for Deep Neural Network inference.
异构 MPSoC 架构上并发应用的运行时可重配置总线仲裁
DOI：
10.1109/dsd.2014.105
发表时间：
2014
期刊：
2014 17th Euromicro Conference on Digital System Design
影响因子：
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作者：
É. Sousa;D. Gangadharan;F. Hannig;J. Teich
通讯作者：
J. Teich