Coherency for multiprocessor virtual address caches
Coherency for multiprocessor virtual address caches
复制标题
多处理器虚拟地址缓存的一致性
DOI：
--
复制
发表时间：
1987
期刊：
影响因子：
--
通讯作者：
J. Goodman
中科院分区：
文献类型：
--
作者：
J. Goodman
描述了一种多处理器高速缓冲存储器系统，其基于虚拟地址向处理器提供数据，但是在主存储器中跨高速缓存和跨虚拟地址空间保持一致性。相同或不同地址空间中的页面可以被映射以共享单个物理页面。相同的硬件用于维护缓存之间和虚拟地址之间的一致性。定义了三种不同的缓存“块”概念：（1）向/从主存储器传输数据的单元，（2）维护标签信息的单元，以及（3）维护一致性的单元。这些块大小之间的关系进行了探讨，它表明，它们可以独立优化。结果表明，使用大的地址块的结果在低开销的虚拟地址缓存。
A multiprocessor cache memory system is described that supplies data to the processor based on virtual addresses, but maintains consistency in the main memory, both across caches and across virtual address spaces. Pages in the same or different address spaces may be mapped to share a single physical page. The same hardware is used for maintaining consistency both among caches and among virtual addresses. Three different notions of a cache "block" are defined: (1) the unit for transferring data to/from main storage, (2) the unit over which tag information is maintained, and (3) the unit over which consistency is maintained. The relation among these block sizes is explored, and it is shown that they can be optimized independently. It is shown that the use of large address blocks results in low overhead for the virtual address cache.