Interconnect modeling and optimization in deep sub-micron technologies
Interconnect modeling and optimization in deep sub-micron technologies
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发表时间：
2002
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通讯作者：
P. Sotiriadis
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作者：
P. Sotiriadis
互连将是未来几年深亚微米技术的主要瓶颈。本论文从功耗和传输速度的角度讨论了通信方面。通过深亚微米技术总线的数据传输相关的能量消耗模型的推导。该模型被用来估计作为一个功能的过渡活动矩阵，数量概括的个别线路的过渡活动因素的总线的功耗。一个信息理论的框架已经发展到研究速度（每单位时间的操作数）和每操作的情况下，同步数字系统的能量消耗之间的关系。该理论为我们提供了以一定速率处理或传递信息所需的每个输入信息比特的基本最小能量。一个大类的非线性编码方案进行检查，导致显着的功率降低。这个类包含所有具有连接的有限状态机形式的编码方案。为了降低功耗，开发了一种适合于深亚微米总线的电荷回收技术。它示出，对于大总线功率可以减少两个因素。一个有效的模块化电路实现，展示了该技术的实用性和其显着的净功耗降低。介绍了总线上的速度编码。这种新颖的想法是基于这样一个事实，即深亚微米总线中的线路之间的耦合意味着不同的转换需要不同的时间来完成。通过只允许"快速"转换发生，我们可以增加总线的时钟频率。这种受限总线的组合容量是数据可以传输的理论最大速率。虽然这个速率低于原始总线的速率，但我们可以更快地为受限总线计时。事实证明，净数据传输速度可以显著高于原始总线，在某些情况下高出120%。介绍了一种估计每次转换所需时间的方法。HSPICE和MATLAB仿真的结果进行了比较，并被证明是保守的。使用这些估计，根据它们完成的速度对转换进行分类。推导了编码速度的基本理论极限。总线的有效速度的增加估计为线路的数量和它们之间的耦合的函数。最后，提出了一类实用的速度编码方案，称为差分RLL（1，∞）方案。（副本可从麻省理工学院图书馆，RM。14 - 0551，剑桥，MA 02139 - 4307。电话：617 - 253 - 5668;传真：617 - 253 - 1690。）（摘要由UMI缩短。）
Interconnect will be a major bottleneck for deep sub-micron technologies in the years to come. This dissertation addresses the communication aspect from a power consumption and transmission speed perspective. A model for the energy consumption associated with data transmission through deep sub-micron technology buses is derived. The model is used to estimate the power consumption of the bus as a function of the Transition Activity Matrix, a quantity generalizing the transition activity factors of the individual lines. An information theoretic framework has been developed to study the relation between speed (number of operations per time unit) and energy consumption per operation in the case of synchronous digital systems. The theory provides us with the fundamental minimum energy per input information bit that is required to process or communicate information at a certain rate. A large class of nonlinear coding schemes is examined that leads to significant power reduction. This class contains all encoding schemes that have the form of connected Finite State Machines. For power reduction, a charge recycling technique appropriate for deep sub-micron buses is developed. It is shown that for large buses power can be reduced by a factor of two. An efficient modular circuit implementation is presented that demonstrates the practicality of the technique and its significant net power reduction. Coding for speed on the bus is introduced. This novel idea is based on the fact that coupling between the lines in a deep sub-micron bus implies that different transitions require different amounts of time to complete. By allowing only “fast” transitions to take place, we can increase the clock frequency of the bus. The combinatorial capacity of such a constrained bus is the theoretical maximum rate that data can be transmitted. While this rate is less than that of the original bus, we can clock the constrained bus faster. It turns out that the net data transmission speed can be significantly higher than that of the original bus, in some cases 120% higher. A methodology to estimate the amount of time each transition requires is introduced. The results are compared to HSPICE and MATLAB simulations and are shown to be conservative. Using these estimates the transitions are classified according to how fast they are completed. The fundamental theoretical limits of Coding For Speed are derived. The increase of the effective speed of the bus is estimated as a function of the number of lines and the coupling between them. Finally, a class of practical coding schemes for speed, termed Differential RLL(1, ∞) schemes, is presented. (Copies available exclusively from MIT Libraries, Rm. 14-0551, Cambridge, MA 02139-4307. Ph. 617-253-5668; Fax 617-253-1690.) (Abstract shortened by UMI.)