VLSI Architecture for Layered Decoding of QC-LDPC Codes With High Circulant Weight
VLSI Architecture for Layered Decoding of QC-LDPC Codes With High Circulant Weight
复制标题
高循环权重QC-LDPC码分层解码的VLSI架构
DOI：
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发表时间：
2013
影响因子：
2.8
通讯作者：
Joseph R. Cavallaro
中科院分区：
文献类型：
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作者：
Yang Sun;Joseph R. Cavallaro
在这个简短的，我们提出了一个高吞吐量的分层解码器架构，以支持更广泛的家庭准循环低密度奇偶校验（QC-LDPC）码，其奇偶校验矩阵构造从阵列的循环子矩阵。每个非零循环子矩阵是K个循环移位单位矩阵的叠加，其中循环权K ≥ 1。我们提出了一种新的分层解码器结构，以支持任何循环重量的QC-LDPC码。提出了一种分块串行译码结构，该结构逐块处理一层奇偶校验矩阵，其中每个分块是一个Z×Z循环矩阵，循环权为K。在案例研究中，我们展示了中国移动的多媒体广播（CMMB）标准，这是台积电65纳米CMOS工艺合成的LDPC解码器设计。CMMB LDPC解码器的核心面积为3.9 mm 2，经过15次迭代，最大吞吐量达到1.1 Gb/s。
In this brief, we propose a high-throughput layered decoder architecture to support a broader family of quasicyclic low-density parity-check (QC-LDPC) codes, whose parity-check matrices are constructed from arrays of circulant submatrices. Each nonzero circulant submatrix is a superposition of K cyclic-shifted identity matrices, where the circulant weight K ≥ 1. We propose a novel layered decoder architecture to support QC-LDPC codes with any circulant weight. We present a block-serial decoding architecture which processes a layer of a parity check matrix block by block, where each block is a Z×Z circulant matrix with a circulant weight of K. In the case study, we demonstrate an LDPC decoder design for the China Mobile Multimedia Broadcasting (CMMB) standard, which was synthesized for a TSMC 65-nm CMOS technology. With a core area of 3.9 mm2, the CMMB LDPC decoder achieves a maximum throughput of 1.1 Gb/s with 15 iterations.