Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors
Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors
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DOI：
10.1109/tvlsi.2018.2884646
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发表时间：
2019-03-01
影响因子：
2.8
通讯作者：
Kumar, Akash
中科院分区：
文献类型：
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作者：
Rai, Shubham;Trommer, Jens;Kumar, Akash
为了评估新兴纳米技术的可行性和实用性，电路设计方面的早期评估是必不可少的。可重构纳米技术，如基于硅或锗纳米线的可重构场效应晶体管，作为实现每个计算单元的多种功能的合适原语具有很大的前景。然而，当直接应用这种新兴的纳米技术时，当代的CMOS电路设计往往会导致次优的设计。例如，我们的两个示范性设计分别获得了31%和71%的大面积。因此，需要提供量身定制的电路设计的新方法，以真正利用这些可重构纳米技术的令人兴奋的功能集。为此，我们提出了基于可重构纳米线技术的六个功能增强的逻辑门，并将这些逻辑门用于高效的电路设计。我们对一个可重构多功能电路进行了详细的比较研究，结果表明，与参考设计相比，该电路的时延(20.14%)、面积(32.40%)和活跃度(40%)具有更好的归一化性能。在此基础上，提出了一种基于硅纳米线可重构FET的1位算术逻辑单元的新设计，其面积、归一化电路延迟和活动性分别比当前的CMOS版提高了30%、34%和36%。
An early evaluation in terms of circuit design is essential in order to assess the feasibility and practicability aspects for emerging nanotechnologies. Reconfigurable nanotechnologies, such as silicon or germanium nanowire-based reconfigurable field-effect transistors, hold great promise as suitable primitives for enabling multiple functionalities per computational unit. However, contemporary CMOS circuit designs when applied directly with this emerging nanotechnology often result in suboptimal designs. For example, 31% and 71% larger area was obtained for our two exemplary designs. Hence, new approaches delivering tailored circuit designs are needed to truly tap the exciting feature set of these reconfigurable nanotechnologies. To this effect, we propose six functionally enhanced logic gates based on a reconfigurable nanowire technology and employ these logic gates in efficient circuit designs. We carry out a detailed comparative study for a reconfigurable multifunctional circuit, which shows better normalized circuit delay (20.14%), area (32.40%), and activity as the power metric (40%) while exhibiting similar functionality as compared with the CMOS reference design. We further propose a novel design for a 1-bit arithmetic logic unit-based on silicon nanowire reconfigurable FETs with the area, normalized circuit delay, and activity gains of 30%, 34%, and 36%, respectively, as compared with the contemporary CMOS version.