Integrated and automated design-for-testability implementation for cell-based ICs
Integrated and automated design-for-testability implementation for cell-based ICs
复制标题
基于单元的 IC 的集成和自动化可测试性设计实现
DOI：
10.1109/ats.1997.643946
复制
发表时间：
1997
期刊：
影响因子：
--
通讯作者：
Masaaki Yoshida
中科院分区：
文献类型：
--
作者：
Toshinobu Ono;Kazuo Wakui;Hitoshi Hikima;Yoshiyuki Nakamura;Masaaki Yoshida
本文介绍了几种基于单元的集成电路的可测性设计(DFT)技术。在基于单元的IC设计中，嵌入式内核经常与用户定义的随机逻辑一起使用。嵌入式内核的存在使得芯片级测试变得更加困难和复杂。根据目标器件的不同，有选择地采用各种测试方法，如测试总线法、内部和边界扫描法以及内建自测试法。描述了用于实际基于单元的ASIC设计的那些DFT方法的结构以及它们在样本芯片中的开销。还解释了它们如何有效地集成和自动化。
This paper presents several design-for-testability (DFT) techniques for cell-based ICs. In the design of cell-based ICs, embedded cores are often used along with the user defined random logic. The existence of embedded cores makes chip level testing more difficult and complicated. Various test methods, such as test bus, internal and boundary scan, and BIST are selectively employed according to the target devices. The structures of those DFT methods being used for actual cell-based ASIC designs are described with their overhead in sample chips. How they are effectively integrated and automated is also explained.