Dynamic Lottery Bus Arbiter for Shared Bus System on Chip: A Design Approach with VHDL
Dynamic Lottery Bus Arbiter for Shared Bus System on Chip: A Design Approach with VHDL
复制标题
片上共享总线系统的动态彩票总线仲裁器：一种采用 VHDL 的设计方法
DOI：
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发表时间：
2008
期刊：
影响因子：
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通讯作者：
P. Bajaj
中科院分区：
文献类型：
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作者：
Neeta Doifode;D. Padole;P. Bajaj
片上通信架构在决定片上系统（SoC）设计的整体性能方面发挥着重要作用。在SoC的资源共享机制中，通信架构应该灵活，以在广泛的流量范围内提供高性能。传统的SoC架构通常采用基于优先级或时分多址(TDMA)的通信架构。然而，这些技术通常是不够的。在前者中，低优先级组件可能会遭受饥饿，而高优先级组件可能会出现较大的延迟。传统的总线分配算法，例如静态固定优先级和循环法，存在总线饥饿以及由于总线周期内的总线分配延迟而导致的系统性能低等缺陷。本文讨论了片上系统的动态彩票总线仲裁器架构。该架构基于概率总线分配算法，并使用自适应票值方法。该体系结构采用VHDL 进行建模，并给出了一些仿真结果。
On-chip communication architecture plays an important role in determining the overall performance of the system-on-chip (SoC) design. In the recourse sharing mechanism of SoC, the communication architecture should be flexible to offer high performance over a wide range of traffic. Conventional SoC architecture typically employ priority or time division multiple access (TDMA) based communication architecture. However, these techniques are often in adequate. In the former, low priority components may suffer from starvation, while high priority components may have large latency. The conventional bus-distribution algorithms, such as the static fixed priority and the round robin, show several defects that are bus starvation, and low system performance because of bus distribution latency in a bus cycle time. In this paper dynamic lottery bus arbiter architecture for a system on chip is discussed. The architecture is based on a probability bus distribution algorithm and uses an adaptive ticket value method. The architecture is model in VHDL and some of the simulation results are presented.