A Functionality-Based Runtime Relocation System for Circuits on Heterogeneous FPGAs
A Functionality-Based Runtime Relocation System for Circuits on Heterogeneous FPGAs
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基于功能的异构 FPGA 电路运行时重定位系统
DOI：
10.1109/tcsii.2018.2826014
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发表时间：
2018
期刊：
影响因子：
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通讯作者：
T. Arslan
中科院分区：
文献类型：
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作者：
Godwin Enemali;A. Adetomi;G. Seetharaman;T. Arslan
现场可编程门阵列（fpga）上的电路运行时重新定位已被提出，以实现许多理想的功能，包括容错，碎片整理和系统负载平衡。然而，fpga架构组成的变化使得重新定位更具挑战性，这主要是因为fpga变得更加异构。以前和最先进的fpga电路重定位系统仅依赖于直接位流重定位，这需要源和目标资源布局相同，以及访问设计位流进行操作。因此，它们在现代异构芯片上的效率大大降低，并且大多无法应用于知识产权块的加密比特流。在本文中，我们提出了一种电路重定位器，它通过基于功能的重定位方案来增强直接位流重定位。我们使用CORDIC应用程序演示了所提出的技术的可行性，并表明，在本案例研究中，与仅直接位流重定位相比，以较小的内存开销和可管理的重定位时间为代价，可获得重定位次数平均增加2.6倍以上。
Runtime relocation of circuits on field-programmable gate arrays (FPGAs) has been proposed for achieving many desirable features including fault tolerance, defragmentation, and system load balancing. However, the changes in the architectural composition of FPGAs have made relocation more challenging mainly because FPGAs have become more heterogeneous. Previous and state-of-the-art circuit relocation systems on FPGAs have relied only on direct bitstream relocation which requires the source and destination resource layouts to be the same, as well as access to the design bitstream for manipulation. Hence, their efficiency on modern heterogeneous chips greatly reduces, and mostly cannot be applied to encrypted bitstreams of intellectual property blocks. In this brief, we present a circuit relocator which augments direct bitstream relocation with a functionality-based relocation scheme. We demonstrate the feasibility of the proposed technique using a CORDIC application and show that an average of over 2.6-fold increase in the number of relocations can be obtained compared to only direct bitstream relocation at the expense of a small memory overhead and manageable relocation time for this case study.