A 2GHz-to-7.5GHz quadrature clock-generator using digital delay locked loops for multi-standard I/Os in 14nm CMOS
A 2GHz-to-7.5GHz quadrature clock-generator using digital delay locked loops for multi-standard I/Os in 14nm CMOS
复制标题
2GHz 至 7.5GHz 正交时钟发生器，采用数字延迟锁定环，用于 14nm CMOS 中的多标准 I/O
DOI：
10.1109/vlsic.2014.6858375
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发表时间：
2014
期刊：
影响因子：
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通讯作者：
F. O’Mahony
中科院分区：
文献类型：
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作者：
A. Elshazly;A. Balankutty;Yan;Kai Yu;F. O’Mahony
提出了一种使用数字DLL的高度数字化正交时钟发生器，该数字DLL采用数字环路滤波器和数字校准的基于复制的调节器。建议DLL结合了传统架构的模拟和数字环路滤波器的优点，以实现宽范围，高能效，高数字化，高性能的正交时钟发生器。为了抑制电源噪声，我们提出了一种LDO，它结合了快速/慢速路径与复制负载，以实现优于20 dB的抑制，小面积和低功耗。在英特尔的14纳米CMOS工艺制造，建议的数字DLL工作在广泛的输出频率（2GHz至7.5GHz）。在7 GHz下，它实现了176 fsrms/2.7pspp的长期抖动，同时消耗4.4mW。DLL比最先进的设计小4倍，占用0.0024mm2的有效面积。
A highly digital quadrature clock generator using a digital DLL that employs a digital loop filter and digitally-calibrated replica-based regulator is presented. The proposed DLL combines the advantages of both analog and digital loop-filters of conventional architectures to implement a wide-range, energy efficient, highly digital, and high performance quadrature clock generator. To suppress supply-noise, we propose an LDO that combines fast/slow paths with a replica-load to achieve better than 20dB rejection with small area and low power. Fabricated in Intel's 14nm CMOS process, the proposed digital DLL operates over a wide range of output frequencies (2GHz-to-7.5GHz). At 7GHz, it achieves 176fsrms/2.7pspp long-term jitter while consuming 4.4mW. The DLL is 4X smaller than state-of-the art designs and occupies an active area of 0.0024mm2.