Modeling and Mitigating Transient Errors in Logic Circuits
Modeling and Mitigating Transient Errors in Logic Circuits
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DOI：
10.1109/tdsc.2010.26
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发表时间：
2011-07
影响因子：
7.3
通讯作者：
I. Polian;J. Hayes;S. Reddy;B. Becker
中科院分区：
文献类型：
--
作者：
I. Polian;J. Hayes;S. Reddy;B. Becker
在微纳电子学中，由各种环境效应引起的瞬时误差或软误差日益受到关注。我们提出了一个通用的框架，用于建模和减轻数字电路中此类错误的逻辑影响。我们观察到一些错误具有时间限制的影响；系统的输出在几个时钟周期内被破坏，之后它会自动恢复。由于这种错误行为在某些应用中是可以容忍的，即它在系统级不是关键的，所以我们定义临界软错误率(CSER)作为传统SER度量的更现实的替代。为了有效地估计组合逻辑和时序逻辑中与单个节点相关的错误概率，提出了一种与技术无关的简化故障模型--单次瞬时故障(STF)。STF可以用来计算感兴趣的错误和错误的各种其他有用的度量，所需的计算可以利用为(永久)固定错误设计的大量现有方法和工具。作为该方法的一个应用，我们介绍了一种针对暂态故障强化逻辑电路的系统策略。其目标是通过选择用于针对STF进行硬化的节点子集，以最低成本实现所需的CSER水平。给出了节点选择问题的精确算法和近似算法。ISCAS-85和ISCAS-89基准测试套件以及一些大型(数百万门)工业电路的实验证明了该方法的有效性。
Transient or soft errors caused by various environmental effects are a growing concern in micro and nanoelectronics. We present a general framework for modeling and mitigating the logical effects of such errors in digital circuits. We observe that some errors have time-bounded effects; the system's output is corrupted for a few clock cycles, after which it recovers automatically. Since such erroneous behavior can be tolerated by some applications, i.e., it is noncritical at the system level, we define the critical soft error rate (CSER) as a more realistic alternative to the conventional SER measure. A simplified technology-independent fault model, the single transient fault (STF), is proposed for efficiently estimating the error probabilities associated with individual nodes in both combinational and sequential logic. STFs can be used to compute various other useful metrics for the faults and errors of interest, and the required computations can leverage the large body of existing methods and tools designed for (permanent) stuck-at faults. As an application of the proposed methodology, we introduce a systematic strategy for hardening logic circuits against transient faults. The goal is to achieve a desired level of CSER at minimum cost by selecting a subset of nodes for hardening against STFs. Exact and approximate algorithms to solve the node selection problem are presented. The effectiveness of this approach is demonstrated by experiments with the ISCAS-85 and -89 benchmark suites, as well as some large (multimillion-gate) industrial circuits.