Design of Hardware/Software Co-Design Environment Using SpecC-Based Tools
Design of Hardware/Software Co-Design Environment Using SpecC-Based Tools
复制标题
使用基于 SpecC 的工具设计硬件/软件协同设计环境
DOI：
10.1155/2008/180216
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发表时间：
2003
期刊：
影响因子：
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通讯作者：
I. Arita
中科院分区：
文献类型：
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作者：
Yuhei Hayashi;Koichiro Tanaka;Toshinori Sato;I. Arita
可重构逻辑器件（RLD）根据其基本逻辑单元架构分为细粒度和粗粒度两种类型。总的来说，每种架构都有自己的优势。因此，难以在各种应用中实现操作速度和实现区域之间的平衡。在本文中，我们提出了一种可变粒度逻辑单元（VGLC）架构，它由一个4位的涟漪进位加法器与配置存储器位，并开发了一个技术映射工具。VGLC架构的关键特性是可变粒度是分别实现算术和随机逻辑所需的粗粒度和细粒度类型之间的折衷。最后，我们使用新开发的技术映射工具评估了所提出的逻辑单元，与Virtex-4逻辑单元架构相比，该工具将逻辑深度提高了31%，平均减少了55%的配置数据数量。
Reconfigurable logic devices (RLDs) are classified as the fine‐grained or coarse‐grained type based on their basic logic cell architecture. In general, each architecture has its own advantage. Therefore, it is difficult to achieve a balance between the operation speed and implementation area in various applications. In the present paper, we propose a variable grain logic cell (VGLC) architecture, which consists of a 4‐bit ripple carry adder with configuration memory bits and develop a technology mapping tool. The key feature of the VGLC architecture is that the variable granularity is a tradeoff between coarse‐grained and fine‐grained types required for the implementation arithmetic and random logic, respectively. Finally, we evaluate the proposed logic cell using the newly developed technology mapping tool, which improves logic depth by 31% and reduces the number of configuration data by 55% on average, as compared to the Virtex‐4 logic cell architecture.