LETTER Special Section on VLSI Technology toward Frontiers of New Market VLSI Implementation of a 4 × 4-bit Multiplier in a Two Phase Drive Adiabatic Dynamic CMOS Logic
LETTER Special Section on VLSI Technology toward Frontiers of New Market VLSI Implementation of a 4 × 4-bit Multiplier in a Two Phase Drive Adiabatic Dynamic CMOS Logic
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LETTER 关于面向新市场前沿的 VLSI 技术的特别章节 在两相驱动绝热动态 CMOS 逻辑中实现 4 × 4 位乘法器的 VLSI
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发表时间：
2007
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通讯作者：
Nonmember
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作者：
Yasuhiro Takahashi;T. Sekine;M. Yokoyama;Nonmember
绝热逻辑是一种设计低功耗数字VLSI的技术。本文介绍了一种采用两相驱动绝热动态CMOS逻辑（2PADCL）电路的乘法器的设计和VLSI实现。电路的工作和性能已被评估使用4 × 4位2PADCL乘法器在1.2 μm CMOS工艺制造。实验结果表明，该乘法器工作在800 kHz的时钟频率下。在1.5V直流电源电压下，4 × 4位2PADCL乘法器的总功耗为5.19mW。
SUMMARY An adiabatic logic is a technique to design low power digital VLSI’s. This paper describes the design and VLSI implementation of a multiplier using a two phase drive adiabatic dynamic CMOS logic (2PADCL) circuit. Circuit operation and performance have been evaluated using a 4 × 4-bit 2PADCL multiplier fabricated in a 1.2 µm CMOS process. The experimental results show that the multiplier was operated with clock frequencies 800 kHz. The total power dissipation of the 4 × 4-bit 2PADCL multiplier was also 5.19 mW at the 1.5 V DC power supply voltage.