An energy efficient, high speed analog FFT processor for MB-OFDM UWB receivers
An energy efficient, high speed analog FFT processor for MB-OFDM UWB receivers
复制标题
适用于 MB-OFDM UWB 接收器的节能、高速模拟 FFT 处理器
DOI：
--
复制
发表时间：
2014
期刊：
影响因子：
--
通讯作者：
M. Zahabi
中科院分区：
文献类型：
--
作者：
A. Farahmand;M. Zahabi
在本文中，我们提出了一种节能，高速模拟快速傅立叶变换（FFT）处理器的多带正交频分复用（MB-OFDM）超宽带（UWB）系统，虽然它通常适用于许多其他OFDM接收机系统。提出的高速，低功耗FFT架构可以提供更高的吞吐率，通过使用模拟CMOS电流镜结构相比，常见的数字类型。该处理器已设计和模拟使用台积电180 nm CMOS工艺与电源电压为1.8 V的IEEE 802.15.3aUWB接收机的情况下，FFT 128点的计算时间为242.42 ns。FFT处理器的计算时间为24 ns，功耗仅为1.7 mW。通过使用所提出的模拟设计，ADC（模拟数字转换器）将取代一个简单的采样保持（S/H）电路的方式，功耗和复杂度将显着降低。根据该FFT处理器的高速和低功耗特性，它可以用于其它已知标准，例如802.15.3c、802.11ac和802.11ad。
In this paper, we present an energy efficient, and high speed analog fast Fourier transform (FFT) processor for Multi-Band Orthogonal Frequency Division Multiplexing (MB-OFDM) Ultrawideband (UWB) systems, although it is generally applicable to many other OFDM based receiver systems. The proposed high-speed, low power FFT architecture can provide higher throughput rate by using analog CMOS current mirrors structure in comparison to common digital types. The proposed processor has been designed and simulated using TSMC 180 nm CMOS technology with a supply voltage of 1.8 V. In the case of the IEEE 802.15.3aUWB receiver, computation time of FFT 128-point is 242.42 ns. Computation time of our FFT processor is 24 ns and consumes only 1.7 mW. By using the proposed analog design, an ADC (analog to digital converter) will be replaced by a simple sample-and-hold (S/H) circuit in a way that the power consumption and the complexity will be decreased remarkably. According to the high speed and low power consumption properties of this FFT processor, it can be used in other known standards such as 802.15.3c, 802.11ac and 802.11ad.