Reducing memory latency via non-blocking and prefetching caches
Reducing memory latency via non-blocking and prefetching caches
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DOI：
10.1145/143365.143486
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发表时间：
1992-09
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影响因子：
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通讯作者：
Tien-Fu Chen;J. Baer
中科院分区：
文献类型：
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作者：
Tien-Fu Chen;J. Baer
非阻塞缓存和预缓存是两种通过利用处理器计算与数据访问的重叠来隐藏内存延迟的技术。只要遵守依赖性约束，非阻塞缓存就允许执行与缓存未命中同时进行，从而利用未命中后操作。预取缓存生成预取请求，在实际需要数据之前将数据带入缓存，从而允许与前置计算重叠。在本文中，我们评估了这两种基于硬件的方案的有效性。我们提出了一种基于这些方法组合的混合设计。我们还考虑基于编译器的优化来增强非阻塞缓存的有效性。 SPEC 基准的指令级模拟结果表明，硬件预取高速缓存的性能通常优于非阻塞高速缓存。此外，与预取高速缓存相比，非阻塞高速缓存的相对有效性更容易受到内存延迟增加的不利影响。但是，非阻塞高速缓存的性能可以通过编译器优化（例如指令调度和寄存器重命名）来大幅提高。混合设计可以非常有效地减少许多应用程序的内存延迟损失。
Non-blocking caches and prefetehing caches are two techniques for hiding memory latency by exploiting the overlap of processor computations with data accesses. A nonblocking cache allows execution to proceed concurrently with cache misses as long as dependency constraints are observed, thus exploiting post-miss operations, A prefetching cache generates prefetch requests to bring data in the cache before it is actually needed, thus allowing overlap with premiss computations. In this paper, we evaluate the effectiveness of these two hardware-based schemes. We propose a hybrid design based on the combination of these approaches. We also consider compiler-based optimization to enhance the effectiveness of non-blocking caches. Results from instruction level simulations on the SPEC benchmarks show that the hardware prefetching caches generally outperform nonblocking caches. Also, the relative effectiveness of nonblocklng caches is more adversely affected by an increase in memory latency than that of prefetching caches,, However, the performance of non-blocking caches can be improved substantially by compiler optimizations such as instruction scheduling and register renaming. The hybrid design cm be very effective in reducing the memory latency penalty for many applications.