Low-Latency Sequential and Overlapped Architectures for Successive Cancellation Polar Decoder
Low-Latency Sequential and Overlapped Architectures for Successive Cancellation Polar Decoder
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DOI：
10.1109/tsp.2013.2251339
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发表时间：
2013-05
影响因子：
5.4
通讯作者：
Chuan Zhang;K. Parhi
中科院分区：
文献类型：
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作者：
Chuan Zhang;K. Parhi
极化码由于其低的编码和解码复杂度，最近已经成为最有利的容量实现纠错码之一。然而，由于实际应用所需的大的码长，现有的几个连续消除（SC）解码器实现仍然遭受不仅高的硬件成本，而且长的解码延迟。在本文中，数据流图（DFG）的SC解码器推导。一个完整的硬件架构，首先推导出传统的树SC解码器和反馈部分。预计算前瞻技术被用来减少可实现的最小解码延迟。采用子结构共享的方法设计合并处理单元，提高了硬件利用率。为了满足各种应用场景的吞吐量要求，还提出了一种系统的方法来构建不同的重叠SC极化解码器架构。与传统的$N$-bit树SC译码器相比，所提出的重叠结构仅需$（{N} log_{2}{N}）/2$合并PE，就可以实现高达$（N-1）$倍的加速比。所提出的预计算方法对于${N} > 2^{7}$导致延迟减少50%，并且对于$N \leq 2^{7}$减少40%。
Polar codes have recently emerged as one of the most favorable capacityachieving error correction codes due to their low encoding and decoding complexity. However, because of the large code length required by practical applications, the few existing successive cancellation (SC) decoder implementations still suffer from not only high hardware cost but also long decoding latency. In this paper, a data-flow graph (DFG) for the SC decoder is derived. A complete hardware architecture is first derived for the conventional tree SC decoder and the feedback part is presented next. Precomputation look-ahead technique is exploited to reduce the achievable minimum decoding latency. Substructure sharing is used to design a merged processing element (PE) for higher hardware utilization. In order to meet throughput requirements for a diverse set of application scenarios, a systematic approach to construct different overlapped SC polar decoder architectures is also presented. Compared with a conventional $N$-bit tree SC decoder, the proposed overlapped architectures can achieve as high as $(N-1)$ times speedup with only $({N}\log_{2}{N})/2$ merged PEs. The proposed pre-computation approach leads to a 50% reduction in latency for ${N} > 2^{7}$, and 40% reduction for $N \leq 2^{7}$.