A novel low-power full-adder cell with new technique in designing logical gates based on static CMOS inverter
A novel low-power full-adder cell with new technique in designing logical gates based on static CMOS inverter
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DOI：
10.1016/j.mejo.2009.06.005
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发表时间：
2009-10-01
影响因子：
2.2
通讯作者：
Kavehei, O.
中科院分区：
文献类型：
--
作者：
Navi, K.;Foroutan, V.;Kavehei, O.
提出了一种基于CMOS反相器的新型低功耗全加器。该全加器由反相器组成。通用门（例如 NOR、NAND 和 MAJORITY-NOT 门）是通过一组反相器及其非常规实现来实现的。在所提出的设计方法中，消除了耗时的异或门。由于全加器经常用于高性能算术电路的树形结构配置中，因此采用级联仿真结构来在实际应用环境中评估全加器。所研究的电路使用 0.18 μm 和 90 nm CMOS 工艺技术进行了能源效率优化。所提出的全加器具有全摆幅逻辑、平衡输出和强大的输出驱动能力。还观察到，所提出的设计可以在许多情况下使用，特别是当以尽可能低的功耗为目标时。电路布局实现和功能检查已分别使用 Cadence IC 封装和 Synopsys HSpice 完成。 (C) 2009 Elsevier Ltd. 保留所有权利。
A new low-power full-adder based on CMOS inverter is presented. This full-adder is comprised of inverters. Universal gates such as NOR, NAND and MAJORITY-NOT gates are implemented with a set of inverters and non-conventional implementation of them. In the proposed design approach the time consuming XOR gates are eliminated. As full-adders are frequently employed in a tree-structured configuration for high-performance arithmetic circuits, a cascaded simulation structure is employed to evaluate the full-adders in a realistic application environment. The circuits being studied were optimized for energy efficiency using 0.18 mu m and 90 nm CMOS process technologies. The proposed full-adder shows full swing logic, balanced outputs and strong output drivability. It is also observed that the presented design can be utilized in many cases especially whenever the lowest possible power consumption is targeted. Circuits layout implementations and checking their functionality have been done using Cadence IC package and Synopsys HSpice, respectively. (C) 2009 Elsevier Ltd. All rights reserved.