Simulation and optimization of Tri-Gates in a 22 nm hybrid Tri-Gate/planar process
Simulation and optimization of Tri-Gates in a 22 nm hybrid Tri-Gate/planar process
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DOI：
10.1109/ulis.2011.5757974
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发表时间：
2011-03
期刊：
影响因子：
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通讯作者：
T. Baldauf;A. Wei;R. Illgen;S. Flachowsky;T. Herrmann;T. Feudel;J. Hontschel;M. Horstmann;W. Klix;R. Stenzel
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文献类型：
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作者：
T. Baldauf;A. Wei;R. Illgen;S. Flachowsky;T. Herrmann;T. Feudel;J. Hontschel;M. Horstmann;W. Klix;R. Stenzel
通过3-D器件模拟（Sentaurus D-2010）研究了构建到平面22 nm块体工艺中的三栅极结构。平面工艺流程序列通过额外的三栅极图案化进行扩展，但除此之外，所有注入都是共享的，这可以在平面和三栅极CMOS的同时处理中完成。具有相同平面掺杂剂分布的平面和三栅极晶体管的比较示出了三栅极的亚阈值斜率、DIBL和VT滚降的实质性改善。研究了三栅晶体管在不同三栅高度和宽度下的电学行为。三栅极尺寸的大空间在静电和ION-IOFF特性方面优于平面。
A Tri-Gate structure built into a planar 22 nm bulk process was investigated by 3-D device simulations (Sentaurus D-2010). The planar process flow sequence was extended with extra Tri-Gate patterning, but otherwise all implants were shared, as could be done in simultaneous processing of planar and Tri-Gate CMOS. A comparison of planar and Tri-Gate transistors with the same planar dopant profiles shows a substantial improvement of subthreshold slope, DIBL, and VT-rolloff for Tri-Gates. The electrical behavior of the Tri-Gate transistor has been studied for various Tri-Gate heights and widths. A large space of Tri-Gate dimensions outperformed planar in terms of electrostatics and ION-IOFF characteristics.