Reconfigurable FET Approximate Computing-based Accelerator for Deep Learning Applications
Reconfigurable FET Approximate Computing-based Accelerator for Deep Learning Applications
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DOI：
10.1109/iscas46773.2023.10181758
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发表时间：
2023-05
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影响因子：
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通讯作者：
Raghul Saravanan;Sathwika Bavikadi;Shubham Rai;Akash Kumar;Sai Manoj Pudukotai Dinakarrao
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文献类型：
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作者：
Raghul Saravanan;Sathwika Bavikadi;Shubham Rai;Akash Kumar;Sai Manoj Pudukotai Dinakarrao
可重构纳米技术，如硅纳米线场效应晶体管(FET)，是一种很有前途的技术，它不仅有助于降低功耗，而且通过可重构支持多功能。它支持可重新配置，并支持每个计算单元的多种功能。这些特性促使我们设计一种新型的高能效硬件加速器，用于实现包括卷积神经网络(CNN)和深度神经网络(DNN)在内的内存密集型应用。为了加快计算速度，我们设计了乘法和累加(MAC)单元来执行计算。对于MAC的设计，我们采用了硅纳米线可重构FET(RFET)。与传统的CMOS实现相比，RFET的使用降低了近70%的功耗，并减少了执行计算的延迟。为了进一步优化开销和提高存储效率，我们引入了一种新的RFET近似技术。基于RFET的近似加法器降低了功耗、面积和延迟，同时对DNN/CNN的精度影响很小。此外，我们还对不同的结构组合进行了详细的研究，包括CMOS、RFET、精确加法器和近似加法器，以展示所提出的基于RFET的近似加速器的优点。基于RFET的加速器在MNIST数据集上的准确率达到94%，与最先进的硬件加速器体系结构相比，面积、功耗和延迟指标分别减少了93%和73%。
Reconfigurable nanotechnologies such as Silicon Nanowire Field Effect Transistors (FETs) serve as a promising technology that not only facilitates lower power consumption but also supports multi-functionality through reconfigurability. It enables reconfigurability and supports multiple functionalities per computational unit. These features motivate us to design a novel state-of-the-art energy-efficient hardware accelerator for implementing memory-intensive applications including convolutional neural networks (CNNs) and deep neural networks (DNNs). To accelerate the computations, we design Multiply and Accumulate (MAC) units to perform the computations. For the design of MACs, we employ Silicon nanowire reconfigurable FETs (RFETs). The use of RFETs leads to nearly 70% power reduction compared to the traditional CMOS implementation and also reduced latency in performing the computations. Further to optimize the overheads and improve memory efficiency, we introduce a novel approximation technique for RFETs. The RFET-based approximate adders lead to reduced power, area, and delay while having a minimal impact on the accuracy of the DNN/CNN. In addition, we carry out a detailed study of varied combinations of architectures involving CMOS, RFETs, accurate adders, and approximate adders to demonstrate the benefits of the proposed RFET-based approximate acclerator. The proposed RFET-based accelerator achieves an accuracy of 94% on MNIST datasets with 93% and 73%reduction in the area, power and delay metrics respectively compared to the state-of-the-art hardware accelerator architectures.