Multi-core architectures: Complexities of performance prediction and the impact of cache topology
Multi-core architectures: Complexities of performance prediction and the impact of cache topology
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多核架构:性能预测的复杂性和缓存拓扑的影响
DOI:
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发表时间:
2009
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通讯作者:
G. Wellein
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文献类型:
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作者:
Jan Treibig;G. Hager;G. Wellein
The balance metric is a simple approach to estimate the performance of bandwidth-limited loop kernels. However, applying the method to in-cache situations and modern multi-core architectures yields unsatisfactory results. This paper analyzes the in uence of cache hierarchy design on performance predictions for bandwidth-limited loop kernels on current mainstream processors. We present a diagnostic model with improved predictive power, correcting the limitations of the simple balance metric. The importance of code execution overhead even in bandwidth-bound situations is emphasized. Finally we analyze the impact of synchronization overhead on multi-threaded performance with a special emphasis on the in uence of cache topology.