Multi-core architectures: Complexities of performance prediction and the impact of cache topology

Multi-core architectures: Complexities of performance prediction and the impact of cache topology
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多核架构:性能预测的复杂性和缓存拓扑的影响

DOI:
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发表时间:
2009
期刊:
arXiv.org
影响因子:
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通讯作者:
G. Wellein
G. Wellein
中科院分区:
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文献类型:
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作者:
Jan Treibig;G. Hager;G. Wellein

文献摘要

被引文献

相似文献

平衡度量是一种简单的方法来估计带宽有限的环路内核的性能。然而,将该方法应用于高速缓存中的情况和现代多核架构产生不令人满意的结果。本文分析了当前主流处理器上带宽受限的循环内核的Cache层次设计对性能预测的影响。我们提出了一个诊断模型,提高预测能力,纠正简单的平衡度量的局限性。强调了即使在带宽受限的情况下代码执行开销的重要性。最后,我们分析了同步开销对多线程性能的影响,特别强调了缓存拓扑结构的影响。
The balance metric is a simple approach to estimate the performance of bandwidth-limited loop kernels. However, applying the method to in-cache situations and modern multi-core architectures yields unsatisfactory results. This paper analyzes the in uence of cache hierarchy design on performance predictions for bandwidth-limited loop kernels on current mainstream processors. We present a diagnostic model with improved predictive power, correcting the limitations of the simple balance metric. The importance of code execution overhead even in bandwidth-bound situations is emphasized. Finally we analyze the impact of synchronization overhead on multi-threaded performance with a special emphasis on the in uence of cache topology.