ReRAM-Based Processing-in-Memory Architecture for Recurrent Neural Network Acceleration
ReRAM-Based Processing-in-Memory Architecture for Recurrent Neural Network Acceleration
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DOI：
10.1109/tvlsi.2018.2819190
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发表时间：
2018-07
影响因子：
2.8
通讯作者：
Yun Long;Taesik Na;S. Mukhopadhyay
中科院分区：
文献类型：
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作者：
Yun Long;Taesik Na;S. Mukhopadhyay
我们提出了一个递归神经网络（RNN）加速器设计与电阻式随机存取存储器（ReRAM）为基础的内存处理（PIM）架构。与之前基于ReRAM的卷积神经网络加速器不同，我们重新设计了系统，使其适合RNN加速。我们测量系统的吞吐量和能源效率与详细的电路和器件特性。我们的设计实现了可重编程性，并采用RNN友好的流水线来提高系统吞吐量。我们观察到，与图形处理单元基线相比，所提出的系统平均实现了79 {\times}$的计算效率提高。我们的模拟还表明，为了保持高精度和计算效率，读取噪声标准差应小于0.2，器件电阻应至少为1 $\text{M}{\Omega }$，器件写入延迟应最小化。
We present a recurrent neural network (RNN) accelerator design with resistive random-access memory (ReRAM)-based processing-in-memory (PIM) architecture. Distinguished from prior ReRAM-based convolutional neural network accelerators, we redesign the system to make it suitable for RNN acceleration. We measure the system throughput and energy efficiency with the detailed circuit and device characterization. Reprogrammability is enabled with our design, and an RNN friendly pipeline is employed to increase the system throughput. We observe that on average the proposed system achieves $79{\times}$ improvement of computing efficiency compared with graphics processing unit baseline. Our simulation also indicates that to maintain high accuracy and computing efficiency, the read noise standard deviation should be less than 0.2, the device resistance should be at least 1 $\text{M}{\Omega }$ , and the device writes latency should be minimized.