Optimization Techniques for the Efficient Implementation of High-Rate Layered QC-LDPC Decoders
Optimization Techniques for the Efficient Implementation of High-Rate Layered QC-LDPC Decoders
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DOI：
10.1109/tcsi.2016.2612655
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发表时间：
2017-02
期刊：
影响因子：
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通讯作者：
Huang-Chang Lee;Mao-Ruei Li;Jyun-Kai Hu;Po-Chiao Chou;Yeong-Luh Ueng
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文献类型：
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作者：
Huang-Chang Lee;Mao-Ruei Li;Jyun-Kai Hu;Po-Chiao Chou;Yeong-Luh Ueng
对于高速率低密度奇偶校验（LDPC）码，分层解码处理可以重新排序，这样就不需要存储可变校验（V2C）消息的先进先出（FIFO）缓冲区，因此可以最小化内存区域，但代价是增加数据依赖性。本文提出了三种可用于实现高效重排序分层解码器的技术。首先，借助图形着色方法，理论上可以确定所需的V2C符号存储库的最小数量，并设计相应的流水线架构。然后，采用整数线性规划技术，将V2C标识内存库进行排列，使管道停留次数最少，从而提高吞吐量。为了进一步简化解码器，如果使用所提出的改进最小和算法，则不存储第一最小值。通过使用90纳米CMOS技术实现速率为0.905（18396,16644）的QC-LDPC解码器，验证了所提出的技术。当使用所提出的技术时，实现结果表明，在不牺牲错误率性能的情况下，吞吐量与面积比（TAR）增加了58.9%。
For high-rate low-density parity-check (LDPC) codes, layered decoding processing can be reordered such that the first-in-first-out (FIFO) buffer that stores variable-to-check (V2C) messages is not needed and, hence, the memory area can be minimized, but at the cost of increased data dependency. This paper presents three techniques that can be used to implement an efficient reordered layered decoder. First, with the assistance of a graph coloring method, the required minimum number of V2C sign memory banks can be theoretically determined, with the corresponding pipeline architecture also designed. After that, the integer linear programming technique is adopted so as to arrange the V2C sign memory banks in a manner that minimizes the number of pipeline stalls, thereby increasing throughput. In order to further simplify the decoder, the first minimum values are not stored if the proposed modified min-sum algorithm is used. The proposed techniques are demonstrated by implementing a rate-0.905 (18396,16644) QC-LDPC decoder using 90-nm CMOS technology. When using the proposed techniques, implementation results show that the throughput-to-area ratio (TAR) increases by 58.9% without sacrificing error-rate performance.