Optimization of the balance between the gate-drain capacitance and the common source inductance for preventing the oscillatory false triggering of fast switching GaN-FETs
Optimization of the balance between the gate-drain capacitance and the common source inductance for preventing the oscillatory false triggering of fast switching GaN-FETs
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DOI：
10.1109/ecce.2017.8095811
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发表时间：
2017-10
期刊：
影响因子：
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通讯作者：
Rynosuke Matsumoto;K. Umetani;E. Hiraki
中科院分区：
文献类型：
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作者：
Rynosuke Matsumoto;K. Umetani;E. Hiraki
GaN-FET由于其快速开关能力而成为有吸引力的开关器件。然而，它们经常遭受振荡假触发，即在快速切换之后引起的一系列自持重复假触发。本文的目的是为了得到一个设计指令，以防止这种现象。根据先前的研究，发现振荡误触发是由GaN-FET形成的寄生振荡器电路、其寄生电容和布线的寄生电感引起的。通过对振荡条件的分析，阐明了防止振荡误触发的设计要求。因此，平衡栅极-漏极寄生电容和共源极电感以实现适当的比率被发现对于防止振荡误触发是至关重要的。实验成功地支持通过平衡这两个因素来防止这种现象。
GaN-FETs are attractive switching devices for their fast switching capability. However, they often suffer from the oscillatory false triggering, i.e. a series of self-sustaining repetitive false triggering induced after a fast switching. The purpose of this paper is to derive a design instruction to prevent this phenomenon. According to the previous study, the oscillatory false triggering was found to be caused by a parasitic oscillator circuit formed of a GaN-FET, its parasitic capacitance, and the parasitic inductance of the wiring. This paper analyzed the oscillatory condition to elucidate the design requirement to prevent the oscillatory false triggering. As a result, balancing the gate-drain parasitic capacitance and the common source inductance to achieve an appropriate ratio was found to be essential for preventing the oscillatory false triggering. Experiment successfully supported prevention of this phenomenon by balancing these two factors.