Scalable device array for statistical characterization of BTI-related parameters
Scalable device array for statistical characterization of BTI-related parameters
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用于 BTI 相关参数统计表征的可扩展器件阵列
DOI：
10.1109/tvlsi.2016.2638021
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发表时间：
2017
影响因子：
2.8
通讯作者：
Takashi Sato
中科院分区：
文献类型：
--
作者：
Hiromitsu Awano;Shumpei Morita;Takashi Sato
提出了一种器件阵列电路，其可根据所使用的晶体管的数量进行缩放。所提出的阵列有利于准确和同时的偏置电压应用到大量的设备，使其适合于基于测量的统计特性的设备退化，被称为偏置温度不稳定性。使用所提出的阵列，成千上万的晶体管的退化测量是可能的，在一个实际的时间量。实验结果表明，缺陷中心模型可以近似阈值电压漂移（ΔVTH）的统计变化，Δ VTH的变化与晶体管沟道面积成反比。在交流应力条件下的降解变异性也是第一次。
A device array circuit, scalable in terms of the number of transistors used, is proposed. The proposed array facilitates accurate and simultaneous bias voltage application to a large number of devices, making it suitable for the measurement-based statistical characterization of device degradation, known as bias temperature instability. Using the proposed array, the degradation measurement of thousands of transistors is made possible in a practical amount of time. The experimental results show that the defect-centric model can approximate the statistical variation in magnitudes of threshold voltage shifts (ΔVTH) and that the variance of ΔVTHbears an inverse relationship to the channel areas of transistors. The degradation variability under ac stress conditions is also presented for the first time.