A performance-constrained template-based layout retargeting algorithm for analog integrated circuits
A performance-constrained template-based layout retargeting algorithm for analog integrated circuits
复制标题
一种基于性能约束的模拟集成电路布局重定向算法
DOI：
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发表时间：
2010
期刊：
影响因子：
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通讯作者：
Lihong Zhang
中科院分区：
文献类型：
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作者：
Zheng Liu;Lihong Zhang
模拟集成电路的性能对版图寄生效应高度敏感。本文提出了一种改进的基于模板的算法，自动进行性能约束的寄生感知重定向和模拟版图优化。为了实现期望的电路性能，首先确定关于布局寄生效应的性能灵敏度。然后，该算法适用于分段灵敏度模型来控制寄生相关的布局几何形状，通过直接构造一组性能约束的最大性能偏差，由于寄生。制定的问题最终解决了基于图的技术结合混合整数非线性规划。所提出的方法已被纳入寄生感知自动布局优化和重定向工具。它已被证明是有效和高效的，特别是在适应新技术或更新规范的布局设计。
Performance of analog integrated circuits is highly sensitive to layout parasitics. This paper presents an improved template-based algorithm that automatically conducts performance-constrained parasitic-aware retargeting and optimization of analog layouts. In order to achieve desired circuit performance, performance sensitivities with respect to layout parasitics are first determined. Then the algorithm applies a piecewise-sensitivity model to control parasitic-related layout geometries by directly constructing a set of performance constraints subject to maximum performance deviation due to parasitics. The formulated problem is finally solved using graph-based techniques combined with mixed-integer nonlinear programming. The proposed method has been incorporated into a parasitic-aware automatic layout optimization and retargeting tool. It has been demonstrated to be effective and efficient especially when adapting layout design for new technologies or updated specifications.