Ab Initio Investigation of Charge Trapping Across the Crystalline-Si-Amorphous-SiO2 Interface
Ab Initio Investigation of Charge Trapping Across the Crystalline-Si-Amorphous-SiO2 Interface
复制标题
晶体-Si-非晶-SiO2 界面上电荷俘获的从头算研究
DOI：
10.1103/physrevapplied.11.044058
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发表时间：
2019-04-18
影响因子：
4.6
通讯作者：
Wang, Lin-Wang
中科院分区：
文献类型：
--
作者：
Liu, Yue-Yang;Zheng, Fan;Wang, Lin-Wang
从半导体到介电氧化物层中缺陷的电荷捕获过程的精确微观描述对于理解许多微电子器件（例如互补金属氧化物半导体（CMOS）晶体管）以及电化学反应至关重要。不幸的是，大多数目前的微观描述这样的过程是基于经验模型与参数拟合的实验设备的性能结果或简化的近似，如文策尔-克拉默斯-布里渊（WKB）方法。一些关键问题仍然没有答案，包括：是什么控制着电荷跳跃率，缺陷能级与半导体能级之间的耦合强度，还是能量差？跳跃率如何随缺陷-半导体距离衰减？什么是缺陷能级的波动，特别是在非晶半导体中？这些问题中的许多可以通过从头计算来回答。然而，迄今为止，很少有从头算研究这个问题，主要是由于从原子结构的建设到大系统计算的技术挑战。在这里，使用的最新进展的计算方法和代码，我们研究的载流子捕获问题，使用密度泛函理论（DFT）的基础上的Heyd-Scuseria-Ernzerhof（HSE）交换相关功能。采用价键随机转换方法构建了c-Si/-SiO2界面原子结构，计算得到的能带偏移与实验结果吻合较好.用Marcus理论计算了跳跃率，揭示了跳跃率与栅电位和缺陷距离的关系，以及非晶结构变化引起的跳跃率波动范围.我们还分析了结果与简单的WKB模型，并发现一个主要的差异，在描述的耦合常数衰减与缺陷半导体距离。我们的研究结果提供了从头计算模拟的见解，这一重要的载流子捕获过程的设备操作。
Accurate microscopic description of the charge-trapping process from semiconductor to defects in the dielectric-oxide layer is of paramount importance for understanding many microelectronic devices such as complementary metal-oxide-semiconductor (CMOS) transistors, as well as electrochemical reactions. Unfortunately, most current microscopic descriptions of such processes are based on empirical models with parameters fitted to experimental device performance results or simplified approximations like the Wentzel-Kramers-Brillouin (WKB) method. Some critical questions are still unanswered, including: What controls the charge-hopping rate, the coupling strength between the defect level to semiconductor level, or the energy difference? How does the hopping rate decay with defect-semiconductor distance? What is the fluctuation of the defect level, especially in amorphous dielectrics? Many of these questions can be answered by ab initio calculations. However, to date, there are few ab initio studies for this problem mainly due to technical challenges from atomic-structure construction to large-system calculations. Here, using the latest advances in calculation methods and codes, we study the carrier-trapping problem using density-functional theory (DFT) based on the Heyd-Scuseria-Ernzerhof (HSE) exchange correlation functional. The valence bond random-switching method is used to construct the crystalline-Si-amorphous-SiO2 (c-Si/-SiO2) interfacial atomic structure, and the HSE yields a band offset that agrees well with experiments. The hopping rate is calculated with the Marcus theory, and the hopping-rate dependences on the gate potential and defect distances are revealed, as well as the range of fluctuation results from amorphous structural variation. We also analyze the result with the simple WKB model and find a major difference in the description of the coupling constant decay with the defect-semiconductor distance. Our results provide the ab initio simulation insights for this important carrier-trapping process for device operation.