Steep-slope hysteresis-free negative capacitance MoS2 transistors
Steep-slope hysteresis-free negative capacitance MoS2 transistors
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DOI：
10.1038/s41565-017-0010-1
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发表时间：
2018-01-01
影响因子：
38.3
通讯作者：
Ye, Peide D.
中科院分区：
文献类型：
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作者：
Si, Mengwei;Su, Chun-Jung;Ye, Peide D.
所谓的玻尔兹曼暴政定义了金属氧化物半导体场效应晶体管（MOSFET）在室温下60 mV dec（-1）的亚阈值斜率的基本电子极限，因此排除了电源电压和总功耗的降低（1，2）。将铁电负电容器添加到MOSFET的栅极堆叠可以提供绕过该基本势垒的有希望的解决方案（3）。同时，二维半导体，如原子级薄的过渡金属二硫属化物，由于其低介电常数和易于集成到无结晶体管拓扑结构中，提供了对沟道的增强的静电控制（4-12）。在这里，我们联合收割机这两个优点，并证明了二硫化钼（MoS 2）的二维陡斜率晶体管的铁电铪锆氧化物层的栅极电介质叠层。该器件在导通和截止状态下均表现出优异的性能，最大漏极电流为510 μ A μ m（-1），亚稳态亚阈值斜率，并且基本上无漏极。在室温下观察到的负微分电阻的二硫化钼负电容FET的负电容由于负漏诱导势垒降低的结果。一个高的导通电流诱导的自加热效应也被观察和研究。
The so-called Boltzmann tyranny defines the fundamental thermionic limit of the subthreshold slope of a metal-oxide-semiconductor field-effect transistor (MOSFET) at 60 mV dec(-1) at room temperature and therefore precludes lowering of the supply voltage and overall power consumption(1,2). Adding a ferroelectric negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier(3). Meanwhile, two-dimensional semiconductors such as atomically thin transition-metal dichalcogenides, due to their low dielectric constant and ease of integration into a junctionless transistor topology, offer enhanced electrostatic control of the channel(4-12). Here, we combine these two advantages and demonstrate a molybdenum disulfide (MoS2) two-dimensional steep-slope transistor with a ferroelectric hafnium zirconium oxide layer in the gate dielectric stack. This device exhibits excellent performance in both on and off states, with a maximum drain current of 510 mu A mu m(-1) and a sub-thermionic subthreshold slope, and is essentially hysteresis-free. Negative differential resistance was observed at room temperature in the MoS2 negative-capacitance FETs as the result of negative capacitance due to the negative drain-induced barrier lowering. A high on-current-induced self-heating effect was also observed and studied.