Hardware-software co-design of an iris recognition algorithm

Hardware-software co-design of an iris recognition algorithm
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虹膜识别算法的软硬件协同设计

DOI：
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发表时间：
2011
期刊：
IET Information Security
影响因子：
1.4
通讯作者：
E. Cantó
E. Cantó
中科院分区：
计算机科学4区
文献类型：
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作者：
Mariano López;J. Daugman;E. Cantó

文献摘要

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本文描述了一种基于 硬件软件协同设计。该系统架构由一个通用的32- 位微处理器和几个从协处理器， 计算。整个虹膜识别算法已经在一个低成本的 Spartan 3 FPGA，与 传统的基于软件的应用程序。实验结果表明， 在40 MHz的速度下，从640 x480的图像中在不到523 ms的时间内获得IrisCode 像素，这只是软件解决方案在 嵌入在架构中的相同微处理器。
This paper describes the implementation of an iris recognition algorithm based on hardware-software co-design. The system architecture consists of a general-purpose 32- bit microprocessor and several slave coprocessors that accelerate the most intensive calculations. The whole iris recognition algorithm has been implemented on a low-cost Spartan 3 FPGA, achieving significant reduction in execution time when compared to a conventional software-based application. Experimental results show that with a clock speed of 40 MHz, an IrisCode is obtained in less than 523 ms from an image of 640x480 pixels, which is just 20% of the total time needed by a software solution running on the same microprocessor embedded in the architecture.