Implementation of SIMD vision chip with 128/spl times/128 array of analogue processing elements
Implementation of SIMD vision chip with 128/spl times/128 array of analogue processing elements
复制标题
具有 128/spl 次/128 模拟处理元件阵列的 SIMD 视觉芯片的实现
DOI：
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发表时间：
2005
期刊：
影响因子：
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通讯作者：
P. Dudek
中科院分区：
文献类型：
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作者：
P. Dudek
本文介绍了 SIMD 电流模式模拟矩阵处理器架构的最新实现。 SCAMP-3 视觉芯片采用 0.35 微米 CMOS 技术制造，包含 128/spl 次/128 个通用可编程处理器/像素阵列。概述了芯片的架构并考虑了实现问题。介绍了模拟寄存器的电路设计，讨论了模拟处理元件的布局，并概述了控制信号驱动器和读出电路的设计。
This paper presents the latest implementation of the SIMD current-mode analogue matrix processor architecture. The SCAMP-3 vision chip has been fabricated in a 0.35 micrometre CMOS technology and comprises a 128/spl times/128 general-purpose programmable processor-per-pixel array. The architecture of the chip is overviewed and implementation issues are considered. The circuit design of the analogue register is presented, the layout of the analogue processing element is discussed and the design of control-signal drivers and readout circuitry is overviewed.