Power, Performance, and Area Benefit of Monolithic 3D ICs for On-Chip Deep Neural Networks Targeting Speech Recognition

Power, Performance, and Area Benefit of Monolithic 3D ICs for On-Chip Deep Neural Networks Targeting Speech Recognition
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DOI:
10.1145/3273956
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发表时间:
2018-11
期刊:
ACM Journal on Emerging Technologies in Computing Systems (JETC)
影响因子:
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通讯作者:
Kyungwook Chang;Deepak Kadetotad;Yu Cao;Jae-sun Seo;S. Lim
Kyungwook Chang;Deepak Kadetotad;Yu Cao;Jae-sun Seo;S. Lim
中科院分区:
其他
文献类型:
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作者:
Kyungwook Chang;Deepak Kadetotad;Yu Cao;Jae-sun Seo;S. Lim

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近年来,深度学习已广泛应用于各种现实世界的识别任务。除了识别准确性,能源效率和速度(即性能)也是在边缘设备中实现本地智能的其他重大挑战。本文以语音识别为测试载体,研究了采用单片三维集成电路(M3D)技术进行深度学习硬件设计的问题。M3D最近已被证明是解决高级技术节点中的功率、性能和面积(PPA)扩展挑战的领先竞争者之一。我们的研究涵盖了DNN硬件实施中的关键参数对其性能和能效的影响,包括DNN架构选择、底层工作负载和M3D设计中的层分区选择。我们的布局后M3D设计与硬件高效的稀疏算法相结合,实现了传统2D IC无法实现的节能和性能提升。实验结果表明,M3D具有22.3%的等性能节能和6.2%的性能提升,有力地证明了它作为DNN ASIC解决方案的资格。我们进一步介绍了M3D DNN的体系结构和物理设计指南,以最大限度地发挥其优势。
In recent years, deep learning has become widespread for various real-world recognition tasks. In addition to recognition accuracy, energy efficiency and speed (i.e., performance) are other grand challenges to enable local intelligence in edge devices. In this article, we investigate the adoption of monolithic three-dimensional (3D) IC (M3D) technology for deep learning hardware design, using speech recognition as a test vehicle. M3D has recently proven to be one of the leading contenders to address the power, performance, and area (PPA) scaling challenges in advanced technology nodes. Our study encompasses the influence of key parameters in DNN hardware implementations towards their performance and energy efficiency, including DNN architectural choices, underlying workloads, and tier partitioning choices in M3D designs. Our post-layout M3D designs, together with hardware-efficient sparse algorithms, produce power savings and performance improvement beyond what can be achieved using conventional 2D ICs. Experimental results show that M3D offers 22.3% iso-performance power saving and 6.2% performance improvement, convincingly demonstrating its entitlement as a solution for DNN ASICs. We further present architectural and physical design guidelines for M3D DNNs to maximize the benefits.