HCDN: Hybrid-Mode Clock Distribution Networks
HCDN: Hybrid-Mode Clock Distribution Networks
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HCDN：混合模式时钟分配网络
DOI：
10.1109/tcsi.2018.2866224
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发表时间：
2019
期刊：
影响因子：
--
通讯作者：
Matthew R. Guthaus
中科院分区：
文献类型：
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作者：
Riadul Islam;Matthew R. Guthaus
我们提出了一种新的混合时钟分配方案，使用全局电流模式和本地电压模式（VM）时钟分配高性能的时钟信号，降低功耗。为了实现混合时钟，我们提出了两个新的电流-电压转换器。该变换器是基于放大器和电流镜电路的简单电流接收电路。全局时钟是无缓冲的，依赖于电流而不是电压，这降低了抖动。本地VM网络提高了与传统CMOS逻辑的兼容性。与传统的VM时钟相比，混合时钟分配网络在对称网络中的平均功耗降低了29%，抖动引起的偏斜降低了54%。为了有效地使用混合时钟，我们提出了一种方法来确定最佳的集群大小和所需的接收器电路的数量，我们使用ISPD 2009，ISPD 2010和ISCAS 89测试台网络演示。在1-2-GHz的时钟频率，所提出的方法使用高达45%和42%的低功耗相比，综合缓冲VM计划使用ISPD 2009和ISPD 2010测试台，分别。此外，建议的混合时钟方案节省高达50%和59%的功率相比，缓冲计划使用ISCAS 89基准电路在1-和2-GHz的时钟频率，分别。
We propose a new hybrid clock distribution scheme that uses global current-mode and local voltage-mode (VM) clocking to distribute a high-performance clock signal with reduced power consumption. In order to enable hybrid clocking, we propose two new current-to-voltage converters. The converters are simple current receiver circuits based on amplifier and current-mirror circuits. The global clocking is bufferless and relies on current rather than voltage, which reduces the jitter. The local VM network improves compatibility with traditional CMOS logic. The hybrid clock distribution network exhibits 29% lower average power and 54% lower jitter-induced skew in a symmetric network compared to traditional VM clocks. To use hybrid clocking efficiently, we present a methodology to identify the optimal cluster size and the number of required receiver circuits, which we demonstrate using the ISPD 2009, ISPD 2010, and ISCAS89 testbench networks. At 1–2-GHz clock frequency, the proposed methodology uses up to 45% and 42% lower power compared to a synthesized buffered VM scheme using ISPD 2009 and ISPD 2010 testbenches, respectively. In addition, the proposed hybrid clocking scheme saves up to 50% and 59% of power compared to a buffered scheme using the ISCAS89 benchmark circuit at 1- and 2-GHz clock frequency, respectively.