Improved Design of 1 T Charge-Modulation Pixel Structure for Small-Size and Low-Dark-Current Achievements
Improved Design of 1 T Charge-Modulation Pixel Structure for Small-Size and Low-Dark-Current Achievements
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1T电荷调制像素结构改进设计，实现小尺寸、低暗电流
DOI：
10.1109/jssc.2002.804347
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发表时间：
2007
期刊：
影响因子：
--
通讯作者：
B. Deschamps
中科院分区：
文献类型：
--
作者：
A. Tournier;F. Roy;G. Lu;B. Deschamps
提出了一种1 T（单晶体管）电荷调制像素结构的环栅设计。它消除了使用STI（浅沟槽隔离）来避免串扰的需要。这使得能够实现更小的像素尺寸和/或更高的填充因子。它还通过限制外围漏电流贡献和最小化带间隧穿效应来降低暗电流。采用0.13μ mCMOS工艺设计了一个集成1.4μ m间距、50%填充因子像素阵列的测试芯片。将实测的像素特性与之前的2.2μmpitch、46%填充因子设计（同样采用0.13μm CMOS工艺）进行了比较。结果表明，1.4μmpitch环栅像素的转换增益（CG）有所提高，而满阱容量（FWC）有所降低。它还显示了暗电流，时间噪声和FPN的显着减少。由此产生的信噪比超过FWC的退化，这也提高了动态范围。
A ring-gate design of 1T (single-transistor) chargemodulation pixel structure is proposed. It obviates the need to employ STI (shallow trench isolation) for avoiding crosstalk. This enables achievements of smaller pixel size and/or higher fill factor. It also reduces dark current by limiting peripheral leakage current contribution and minimizing band-to-band tunneling effect. A test chip integrating an array of 1.4μm-pitch, 50%-fill-factor pixels is designed in a 0.13μm CMOS technology. The measured pixel characteristics are compared with those from a 2.2μmpitch, 46%-fill-factor previous design (also in a 0.13μm CMOS process). The comparison shows that the 1.4μmpitch ring-gate pixel has an improved conversion gain (CG) and a degraded full well capacity (FWC). It also shows substantial reductions on dark current, temporal noise and FPN. The resulting signal-to-noise ratio outweighs degradation of FWC, which also improves dynamic range.