Automatic data path extraction in large-scale register-transfer level designs
Automatic data path extraction in large-scale register-transfer level designs
复制标题
大规模寄存器传输级设计中的自动数据路径提取
DOI：
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复制
发表时间：
2014
期刊：
影响因子：
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通讯作者：
D. Edwards
中科院分区：
文献类型：
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作者：
Wei Song;J. Garside;D. Edwards
大规模寄存器传输级设计中数据通路的提取在同步电路的自动验证和异步电路的综合中有重要的应用。当前的工具依赖于用户提供数据/控制分区或使用状态空间分析来提取数据路径。由于状态空间的爆炸，后一种方法只能用于小的设计。针对这一问题，提出了一种图形搜索和裁剪的方法，可以在大规模设计中提取数据路径。设计首先被转换成图形表示，即信号级数据流图（DFG），以揭示信号之间的连接。通过估计这些连接的类型（控制或数据），线性搜索算法可以删除图中所有与控制相关的信号，从而有效地产生具有纯数据路径的DFG。结果表明，该方法可以在几秒钟内提取出大规模设计的数据路径。
Extracting data paths in large-scale register-transfer level designs has important usage in automatic verification of synchronous circuits and synthesis of asynchronous circuits. Current tools rely on users to provide the data/control partition or use state-space analyses to extract data paths. Due to the explosion of state-space, the latter method can be used in only small designs. To resolve this problem, a graphic search and trim method, which can extract data paths in large scale designs, is presented. A design is first translated into a graphic representation, namely a signal-level data flow graph (DFG), to reveal the connections between signals. By estimating the types (control or data) of these connections, a linear search algorithm can then remove all control-related signals in the graph, which effectively produces a DFG with pure data paths. Results show that this method extracts data paths of large scale designs in seconds.