Transistor sizing and folding techniques for radiation hardening
Transistor sizing and folding techniques for radiation hardening
复制标题
用于辐射硬化的晶体管尺寸和折叠技术
DOI：
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发表时间：
2009
期刊：
影响因子：
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通讯作者：
R. Reis
中科院分区：
文献类型：
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作者：
F. Kastensmidt;T. Assis;I. Ribeiro;G. Wirth;L. Brusamarello;R. Reis
利用电路和器件模拟评估了晶体管尺寸和折叠技术减轻CMOS电路中SET的效率。根据电离粒子的LET，这些方法可以或多或少地过滤SET。基于电路和器件模拟的结果，提出了一种能够减小SET效应的新技术。该方法结合了晶体管尺寸、折叠和电阻。该技术已应用于一系列反相器和SRAM单元中。
The efficiency of transistor sizing and folding techniques to mitigate SET in CMOS circuits is evaluated using circuit and device simulations. According to the LET of the ionizing particle, the SET can be more or less filtered by these methods. Based on the results of the circuit and device simulations, a novel technique able to reduce the SET effect is proposed. The method combines transistor sizing, folding and resistors. The technique was applied in a chain of inverters and SRAM cell.