A memory efficient belief propagation decoder for polar codes
A memory efficient belief propagation decoder for polar codes
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DOI：
10.1109/cc.2015.7112042
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发表时间：
2015-06
影响因子：
4.1
通讯作者：
Jin Sha;Xing Liu;Zhongfeng Wang;Xiaoyang Zeng
中科院分区：
文献类型：
--
作者：
Jin Sha;Xing Liu;Zhongfeng Wang;Xiaoyang Zeng
极化码由于其容量实现特性而近来变得越来越流行。本文提出了一种极化码的存储高效的阶段组合置信传播（BP）译码器设计。首先，我们简要回顾了传统的BP译码算法。提出了一种将相邻两级合并为一级的分段组合BP译码算法，并给出了相应的置信度信息更新规则。在此基础上，设计了一种存储效率高的极化BP译码器。所演示的解码器设计实现了50%的内存和解码延迟减少一些组合逻辑复杂性开销的成本。该解码器是在台积电45 nm低功耗CMOS工艺下综合的。当码长N=216时，译码器面积为14.2mm2，吞吐率为0.96Gb/s，比传统的译码器面积减少了51.5%。
Polar codes have become increasingly popular recently because of their capacity achieving property. In this paper, a memory efficient stage-combined belief propagation (BP) decoder design for polar codes is presented. Firstly, we briefly reviewed the conventional BP decoding algorithm. Then a stage-combined BP decoding algorithm which combines two adjacent stages into one stage and the corresponding belief message updating rules are introduced. Based on this stage-combined decoding algorithm, a memory-efficient polar BP decoder is designed. The demonstrated decoder design achieves 50% memory and decoding latency reduction in the cost of some combinational logic complexity overhead. The proposed decoder is synthesized under TSMC 45nm Low Power CMOS technology. It achieves 0.96 Gb/s throughput with 14.2mm2 area when code length N=216 which reduces 51.5% decoder area compared with the conventional decoder design.