A Statistical Framework for Estimation of Full-Chip Leakage-Power Distribution Under Parameter Variations
A Statistical Framework for Estimation of Full-Chip Leakage-Power Distribution Under Parameter Variations
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DOI：
10.1109/ted.2007.906960
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发表时间：
2007-10
影响因子：
3.1
通讯作者：
H. Dadgour;Sheng-Chih Lin;K. Banerjee
中科院分区：
文献类型：
--
作者：
H. Dadgour;Sheng-Chih Lin;K. Banerjee
本文提出了一种新的框架，用于精确估计参数变化下芯片的亚阈值和栅极泄漏分布的关键统计参数，同时考虑工艺（P）、温度（T）和电源电压（V）中的管芯内和管芯间变化。对于第一次，温度变化，更重要的是，结（衬底或芯片）温度和泄漏功率之间的耦合已占全芯片泄漏估计方法。在所提出的框架中，而不是精确的泄漏分布轮廓，其统计上重要的参数，如标称值和蔓延，计算。首先，在晶体管级，器件泄漏分量对P-T-V变化的相对灵敏度的定量分析被执行以提取晶体管级变化模型。结果表明，所提出的统计模型，与文献中的其他人相比，表现出更好的协议与BSIM 1模型为基础的模拟。它还表明，不考虑温度变化和温度耦合可能会导致芯片级泄漏估计显着的不准确性。此外，全芯片泄漏功率分布被用来估计泄漏约束下的收益率的变化的影响。计算结果表明，由于芯片内和芯片到芯片的工艺和温度变化，产量显着降低。随后，所提出的框架被应用于复杂逻辑电路的泄漏估计与工艺参数的空间相关性和晶体管堆叠效应的考虑。
This paper presents a novel framework for accurate estimation of key statistical parameters of the subthreshold-and gate-leakage distributions of a chip under parameter variations while considering both within-die and die-to-die variabilities in process (P), temperature (T), and supply voltage (V). For the first time, temperature variations and, more importantly, electrothermal couplings between junction (substrate or die) temperature and leakage power have been accounted for in a full-chip leakage estimation methodology. In the proposed framework, instead of exact leakage distribution profile, its statistically important parameters, such as nominal value and spread, are computed. Initially, at the transistor level, a quantitative analysis of the relative sensitivities of device leakage components to P-T-V variations is performed to extract a transistor-level variation model. It is shown that the proposed statistical model, as compared to others in the literature, shows better agreement with BSIM1 model-based simulations. It is also demonstrated that failing to account for temperature variations and electrothermal couplings can result in significant inaccuracy in chip-level leakage estimation. Furthermore, the full-chip leakage-power distribution is used to estimate the leakage-constrained yield under the impact of variations. The calculations show that yield is significantly lowered due to the within-die and die-to-die process and temperature variations. Subsequently, the proposed framework is applied in the leakage estimation of complex logic circuits with a consideration of spatial correlations of process parameters and transistor stacking effects.