23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme
23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme
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23.2 5Gb/s/pin 8Gb LPDDR4X SDRAM，具有电源隔离 LVSTL 和带 2 芯片 ZQ 校准方案的分体芯片架构
DOI：
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发表时间：
2017
期刊：
影响因子：
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通讯作者：
G. Jin
中科院分区：
文献类型：
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作者：
Chang;Yoon;Jin;Junha Lee;Hye;Kihan Kim;Young;Ho;Jonghyuk Kim;Jong;Seungjun Shin;Hanna Park;Su;Young;Hoon Lee;Kyong;Jae;Hyo;Kyoung;Jung;Soobong Chang;H. Hwang;Du;Yoon;S. Hyun;Joonbae Park;Yoon;Youn;H. Kwon;Seung;T. Oh;Indal Song;Yong;J. Choi;Kwang;Seong;G. Jin
随着对低功率移动的应用（诸如可穿戴设备、智能电话和平板PC）的需求不断增长，低功率移动的DRAM已被确定为低功率系统设计的强制性要求。最近开发的LPDDR 4 [1]由于其架构方法和低电压摆幅端接逻辑（LVSTL），仍然是一种高能效解决方案。然而，对于移动的应用而言，对超出LPDDR 4的增强功率效率的需求仍在增加。在这项工作中，一个5.0Gbp/s/pin的8 Gb LPDDR 4X存储器与电源隔离的低电压摆幅终止逻辑（PI-LVSTL）和一个分裂的芯片架构，以提高功率效率和大规模生产的良率。
With growing demand for low-power mobile applications, such as wearable devices, smart phones and tablet PCs, low-power mobile DRAM has been identified as a mandatory requirement for low-power system designs. The recently developed LPDDR4 [1] is still a power efficient solution because of its architectural approaches and low-voltage-swing terminated logic (LVSTL). However, demand for enhanced power-efficiency beyond LPDDR4 is still increasing for mobile applications. In this work, a 5.0Gbp/s/pin 8Gb LPDDR4X memory with power-isolated low-voltage-swing terminated logic (PI-LVSTL) and a split-die architecture is proposed to enhance power-efficiency and mass production yield.