Design and analysis of dual-rail circuits for security applications
Design and analysis of dual-rail circuits for security applications
复制标题
用于安全应用的双轨电路的设计和分析
DOI：
10.1109/tc.2005.61
复制
发表时间：
2005
影响因子：
3.7
通讯作者：
A. Yakovlev
中科院分区：
文献类型：
--
作者：
D. Sokolov;Julian P. Murphy;A. Bystrov;A. Yakovlev
双轨编码、返回间隔协议和无危险逻辑可用于抵御功率分析攻击，使每个时钟周期消耗的能量与处理的数据无关。标准双轨逻辑使用带有单个间隔器（如全泽洛）的协议，这会产生能量平衡问题。为了解决这些问题，我们采用了两个间隔器；间隔器在相邻时钟周期之间交替使用。这样，无论传输的数据值如何，都能保证所有栅极在每个时钟周期内切换。为了生成这些双轨电路，我们开发了一种自动工具。它能够将同步网表转换为双轨电路，并与工业 CAD 工具相连接。为了评估该方法和工具，我们模拟并比较了基于高级加密标准（AES）的双轨和单轨基准。
Dual-rail encoding, return-to-spacer protocol, and hazard-free logic can be used to resist power analysis attacks by making energy consumed per clock cycle independent of processed data. Standard dual-rail logic uses a protocol with a single spacer, e.g., all-zeros, which gives rise to energy balancing problems. We address these problems by incorporating two spacers; the spacers alternate between adjacent clock cycles. This guarantees that all gates switch in every clock cycle regardless of the transmitted data values. To generate these dual-rail circuits, an automated tool has been developed. It is capable of converting synchronous netlists into dual-rail circuits and it is interfaced to industry CAD tools. Dual-rail and single-rail benchmarks based upon the advanced encryption standard (AES) have been simulated and compared in order to evaluate the method and the tool.