Extending High-Level Synthesis for Task-Parallel Programs
Extending High-Level Synthesis for Task-Parallel Programs
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DOI：
10.1109/fccm51124.2021.00032
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发表时间：
2020-09
期刊：
影响因子：
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通讯作者：
Yuze Chi;Licheng Guo;Young-kyu Choi;Jie Wang;J. Cong
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文献类型：
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作者：
Yuze Chi;Licheng Guo;Young-kyu Choi;Jie Wang;J. Cong
基于C/C++/OpenCL的高级综合（HLS）由于其相对于传统寄存器传输级设计方法具有较好的结果质量（QoR）和较短的开发周期，近年来在许多应用领域越来越受到现场可编程门阵列（FPGA）加速器的青睐。然而，受限于顺序C语义，在许多其他应用领域中采用相同的高效高级编程方法仍然具有挑战性，其中粗粒度任务并行运行并在细粒度级别上相互通信。虽然当前的HLS工具确实支持任务并行程序，但由于可编程性差，在代码开发周期中，由于受限的软件模拟，在正确性验证周期中，以及由于代码生成缓慢，在QoR调优周期中，生产力受到极大限制。这种有限的生产力往往击败HLS的目的，并阻碍程序员采用HLS的任务并行FPGA accelerator.In本文中，我们扩展了HLS的C++语言，并提出了一个全自动化的框架，程序员友好的界面，无约束的软件仿真，并快速分层代码生成，以克服这些限制，并演示如何在HLS任务并行程序可以有效地支持。实验结果表明，基于广泛的现实世界的任务并行程序，平均而言，内核和主机代码的行分别减少了22%和51%，这大大提高了可编程性。正确性验证和迭代QoR调整周期分别大大缩短了3.2倍和6.8倍。我们的工作在https://github.com/UCLA-VAST/tapa/上是开源的。
C/C++/OpenCL-based high-level synthesis (HLS) becomes more and more popular for field-programmable gate array (FPGA) accelerators in many application domains in recent years, thanks to its competitive quality of results (QoR) and short development cycles compared with the traditional register-transfer level design approach. Yet, limited by the sequential C semantics, it remains challenging to adopt the same highly productive high-level programming approach in many other application domains, where coarse-grained tasks run in parallel and communicate with each other at a fine-grained level. While current HLS tools do support task-parallel programs, the productivity is greatly limited in the code development cycle due to the poor programmability, in the correctness verification cycle due to restricted software simulation, and in the QoR tuning cycle due to slow code generation. Such limited productivity often defeats the purpose of HLS and hinder programmers from adopting HLS for task-parallel FPGA accelerators.In this paper, we extend the HLS C++ language and present a fully automated framework with programmer-friendly interfaces, unconstrained software simulation, and fast hierarchical code generation to overcome these limitations and demonstrate how task-parallel programs can be productively supported in HLS. Experimental results based on a wide range of real-world task-parallel programs show that, on average, the lines of kernel and host code are reduced by 22% and 51%, respectively, which considerably improves the programmability. The correctness verification and the iterative QoR tuning cycles are both greatly shortened by 3.2× and 6.8×, respectively. Our work is open-source at https://github.com/UCLA-VAST/tapa/.