An Algorithm for the Design of Low-Power Hardware-Efficient FIR Filters
An Algorithm for the Design of Low-Power Hardware-Efficient FIR Filters
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DOI：
10.1109/tcsi.2008.917997
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发表时间：
2008-02
期刊：
影响因子：
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通讯作者：
M. Aktan;A. Yurdakul;Günhan Dündar
中科院分区：
文献类型：
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作者：
M. Aktan;A. Yurdakul;Günhan Dündar
提出了一种设计低功耗、硬件高效的线性相位有限脉冲响应（FIR）滤波器的新算法。该算法在给定滤波器频率响应特性的情况下，找到具有减少的2次幂（SPT）项数目的滤波器系数。该算法是一种基于分支定界的算法，将系数固定在一定的值上。该值是通过使用线性规划找到系数的边界值来确定的。尽管该算法的最坏情况运行时间是指数级的，但它在合理的时间内找到相当好的解决方案的能力使其成为设计低功耗和硬件效率滤波器的理想CAD工具。通过几个设计实例，证明了该算法在SPT项数、设计时间、硬件复杂度和功耗性能等方面优于现有方法。与未优化的Remez系数相比，SPT项的数量减少了30%，比比较的优化方法好20%。与未优化系数相比，平均节电20%，比使用现有方法获得的优化系数高14%。
A novel algorithm for designing low-power and hardware-efficient linear-phase finite-impulse response (FIR) filters is presented. The algorithm finds filter coefficients with reduced number of signed-power-of-two (SPT) terms given the filter frequency response characteristics. The algorithm is a branch-and-bound-based algorithm that fixes a coefficient to a certain value. The value is determined by finding the boundary values of the coefficient using linear programming. Although the worst case run time of the algorithm is exponential, its capability to find appreciably good solutions in a reasonable amount of time makes it a desirable CAD tool for designing low-power and hardware-efficient filters. The superiority of the algorithm on existing methods in terms of SPT term count, design time, hardware complexity, and power performance is shown with several design examples. Up to 30% reduction in the number of SPT terms is achieved over unoptimized Remez coefficients, which is 20% better than compared optimization methods. The average power saving is 20% over unoptimized coefficients, which is up to 14% better than optimized coefficients obtained with existing methods.