DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks
DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks
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DOI：
10.1109/test.2012.6401569
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发表时间：
2012-11
期刊：
影响因子：
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通讯作者：
Sergej Deutsch;B. Keller;V. Chickermane;Subhasish Mukherjee;Navdeep Sood;S. Goel;Ji-Jan Chen;Ashok Mehta;F. Lee;E. Marinissen
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文献类型：
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作者：
Sergej Deutsch;B. Keller;V. Chickermane;Subhasish Mukherjee;Navdeep Sood;S. Goel;Ji-Jan Chen;Ashok Mehta;F. Lee;E. Marinissen
三维(3D)芯片堆叠是一种新兴的集成技术，它在异质集成、芯片间互连密度、性能和能效以及元件尺寸和成品率方面带来了好处。在过去，我们已经描述了对于逻辑上逻辑芯片堆栈，基于芯片级包装器的3D DFT(为测试而设计)体系结构和相应的自动化。逻辑存储堆栈是即将上市的首批3D产品之一。最近，JEDEC发布了可堆叠式宽I/O移动DRAM(Dynamic Random Access Memory，动态随机存取存储器)标准，其中规定了逻辑-存储器接口。该标准包括DRAM存储器中的边界扫描功能。在本文中，我们利用并扩展了逻辑芯片的3D DFT包装器，以便结合其上堆叠的宽I/O动态随机存储器(S)中的边界扫描功能，实现对逻辑存储器互连的测试。使用专用互连ATPG(自动测试模式生成)算法来提供有效且高效的专用测试模式。我们已经在工业设计上验证了我们提出的DFT扩展，并表明支持JEDEC Wide-I/O互连测试的扩展包装器的硅面积成本可以忽略不计。
Three-dimensional (3D) die stacking is an emerging integration technology which brings benefits with respect to heterogeneous integration, inter-die interconnect density, performance, and energy efficiency, and component size and yield. In the past, we have described, for logic-on-logic die stacks, a 3D DfT (Design-for-Test) architecture and corresponding automation, based on die-level wrappers. Memory-on-logic stacks are among the first 3D products that will come to the market. Recently, JEDEC has released a standard for stackable Wide-I/O Mobile DRAMs (Dynamic Random Access Memories) which specifies the logic-memory interface. The standard includes boundary scan features in the DRAM memories. In this paper, we leverage and extend the 3D DfT wrapper for logic dies, such that, in conjunction with the boundary scan features in the Wide-I/O DRAM(s) stacked on top of it, testing the logic-memory interconnects is enabled. A dedicated Interconnect ATPG (Automatic Test Pattern Generation) algorithm is used to deliver effective and efficient dedicated test patterns. We have verified our proposed DfT extension on an industrial design and shown that the silicon area cost of the extended wrapper with JEDEC Wide-I/O interconnect test support is negligible.