Crosstalk reduction for VLSI
Crosstalk reduction for VLSI
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DOI：
10.1109/43.594834
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发表时间：
1997-03
期刊：
影响因子：
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通讯作者：
A. Vittal;M. Marek-Sadowska
中科院分区：
文献类型：
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作者：
A. Vittal;M. Marek-Sadowska
高速电子系统的性能受到耦合噪声等与互连相关的故障模式的限制。我们提出了新的技术来缓解集成电路上信号线之间的耦合所引起的问题。我们证明了前人在耦合噪声约束的版图综合中使用的模型不允许使用几个重要的自由度。这些自由度包括利用动态噪声裕度而不是静态噪声裕度的能力、耦合噪声对驱动强度的依赖性以及使用重叠来降低对噪声的敏感性的可能性。我们推导了耦合噪声积分的表达式和峰值耦合噪声电压的界，与以前工作中使用的电荷共享模型相比，它在精度和保真度方面都有数量级的提高。我们使用新的界限来指导贪婪通道路由器，它在每个阶段处理准确的邻接信息，允许它在需要时引入慢跑或狗腿来降低耦合噪声。实验结果表明，该算法比以往的算法具有更好的性能。在基准实例上，耦合噪声显著降低。
The performance of high-speed electronic systems is limited by interconnect-related failure modes such as coupled noise. We propose new techniques for alleviating the problems caused by coupling between signal lines on integrated circuits. We show that models used by previous work on coupled noise-constrained layout synthesis do not allow the use of several important degrees of freedom. These degrees of freedom include the ability to utilize dynamic noise margins rather than static noise margins, the dependence of coupled noise on drive strength, and the possibility of using overlaps to reduce susceptibility to noise. We derive an expression for the coupled noise integral and a bound for the peak coupled noise voltage which shows order of magnitude improvements in both accuracy and fidelity compared to the charge sharing model used in previous work. We use the new bounds to guide a greedy channel router, which manipulates exact adjacency information at every stage, allowing it to introduce jogs or doglegs when necessary for coupled noise reduction. Experimental results indicate that our algorithm compares favorably to previous work. The coupled noise is significantly reduced on benchmark instances.