An Interlayer Interconnect BIST and Diagnosis Solution for Monolithic 3-D ICs
An Interlayer Interconnect BIST and Diagnosis Solution for Monolithic 3-D ICs
复制标题
适用于单片 3D IC 的层间互连 BIST 和诊断解决方案
DOI：
10.1109/tcad.2019.2935410
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发表时间：
2020
影响因子：
2.9
通讯作者：
K. Chakrabarty
中科院分区：
文献类型：
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作者：
Abhishek Koneru;K. Chakrabarty
与基于硅通孔的3-D集成相比，单片3-D （M3D）集成提供了更高密度的集成。然而，在不显著影响制造成本的情况下，需要在测试方面取得进展来筛选M3D集成中的缺陷。我们提出了一种内置自检（BIST）解决方案来针对层间过孔（ilv）中的短路和打开。在提出的解决方案中，两层界面的扫描单元使用其功能输出和ilv缝合成一个扭环计数器（TRC）。接口寄存器单元启动和捕获测试，测试路径由ilv和多路复用器组成。我们将最小化连接TRC的导线长度的问题映射为在加权二部图中寻找最小代价哈密顿电路的问题。由于加权哈密顿电路问题是np完全的，我们提出了一种求解该问题的启发式算法。我们还提出了一个基于人工神经网络的框架，当芯片未通过所提出的测试时进行诊断。我们通过仿真证明了所提出的BIST解决方案可以检测到所有的开路和短路。我们还通过模拟表明，所提出的诊断框架可以准确地估计ilv缺陷的大小。
Monolithic 3-D (M3D) integration offers higher-density integration compared to 3-D integration based on through-silicon vias. Advances in testing are however needed to screen defects in M3D integration without significantly impacting manufacturing cost. We propose a built-in-self-test (BIST) solution to target shorts and opens in interlayer vias (ILVs). In the proposed solution, scan cells at the interface of two layers are stitched into a twisted-ring counter (TRC) using their functional outputs and ILVs. The interface-register cells launch and capture tests, and a test path consists of ILVs and a multiplexer. We map the problem of minimizing the length of the wires added to stitch the TRC to that of finding a minimum-cost Hamiltonian circuit in a weighted bipartite graph. Since the weighted Hamiltonian circuit problem is NP-Complete, we propose a heuristic algorithm for this problem. We also propose a framework based on artificial neural network to carry out diagnosis when a chip fails the proposed test. We show using simulations that the proposed BIST solution can detect all opens and shorts. We also show using simulations that the proposed diagnosis framework can accurately estimate the size of defects in ILVs.