Standard cell characterization considering lithography induced variations
Standard cell characterization considering lithography induced variations
复制标题
考虑光刻引起的变化的标准电池表征
DOI：
10.1145/1146909.1147111
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发表时间：
2006
期刊：
影响因子：
--
通讯作者：
Jiang Hu
中科院分区：
文献类型：
--
作者：
Ke Cao;S. Dobre;Jiang Hu
随着超大规模集成电路（VLSI）技术向65纳米及更高的方向发展，集成电路的时序和功耗性能越来越受到工艺变化的影响。在实践中，人们经常以与基于工艺角的方法中的随机变化相同的方式来对待变化的系统性分量，其通常根据工艺模型可追踪。因此，过程角模型是不必要的悲观。在本文中，我们提出了一种新的单元表征方法，捕捉光刻引起的栅极长度的变化。提出了一种新的屏蔽单元间光干扰的虚置多晶硅技术。该技术与标准单元一起使用我们的方法来表征，将使当前的设计流程几乎没有任何变化地理解变化。工业设计上的实验结果表明，我们的方法可以减少平均8%-25%的时间变化窗口，功率变化窗口的55%相比，最坏的情况下的方法。对于工业低功耗设计，通过使用根据我们的方法表征的单元，获得了超过300 ps的路径延迟变化减少
As VLSI technology scales toward 65nm and beyond, both timing and power performance of integrated circuits are increasingly affected by process variations. In practice, people often treat systematic components of the variations, which are generally traceable according to process models, in the same way as random variations in process corner based methodologies. Consequently, the process corner models are unnecessarily pessimistic. In this paper, we propose a new cell characterization methodology which captures lithography induced gate length variations. A new technique of dummy poly insertion is suggested to shield inter-cell optical interferences. This technique together with standard cells characterized using our methodology will let current design flows comprehend the variations almost without any changes. Experimental results on industrial designs indicate that, our methodology can averagely reduce timing variation window by 8%-25%, power variation window by 55% when compared to a worst case approach. For an industrial low power design, over 300ps reduction on the path delay variation is obtained by using cells characterized according to our methodology