Hybrid STT-CMOS designs for reverse-engineering prevention
Hybrid STT-CMOS designs for reverse-engineering prevention
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DOI：
10.1145/2897937.2898099
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发表时间：
2016-06
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影响因子：
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通讯作者：
Theodore Winograd;H. Salmani;H. Mahmoodi;K. Gaj;H. Homayoun
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作者：
Theodore Winograd;H. Salmani;H. Mahmoodi;K. Gaj;H. Homayoun
本文通过引入一类对设计逆向工程具有抗性的新型逻辑可重构设计，朝着确保设计的方向迈出了严谨的一步。基于非易失性自旋转移矩（STT）磁性技术，我们引入了一组基本的非易失性可重构查找表（LUT）逻辑组件（基于NV - STT的LUT）。与CMOS相比，基于STT的LUT具有显著不同的特性集，这为增强设计安全性提供了新的机遇，但在功耗、性能和面积方面要与定制CMOS甚至基于SRAM的LUT保持高度竞争力则具有挑战性。为了应对这些挑战，我们提出了几种算法，以便在设计实现过程中用可重构的基于STT的LUT选择并替换定制CMOS门，这样基于STT的组件的功能以及整个设计在任何可管理的时间内都无法确定，从而使任何设计逆向工程攻击都无效。我们对大量标准电路基准进行的研究得出结论：混合STT - CMOS电路对各种类型的攻击具有显著的抗性。此外，选择算法对设计参数约束（包括性能、功耗和面积）的平均影响较小，分别小于3%、8%和3%。
This paper presents a rigorous step towards design-for-assurance by introducing a new class of logically reconfigurable design resilient to design reverse engineering. Based on the non-volatile spin transfer torque (STT) magnetic technology, we introduce a basic set of non-volatile reconfigurable Look-Up-Table (LUT) logic components (NV-STT-based LUTs). STT-based LUT with significantly different set of characteristics compared to CMOS provides new opportunities to enhance design security yet makes it challenging to remain highly competitive with custom CMOS or even SRAM-based LUT in terms of power, performance and area. To address these challenges, we propose several algorithms to select and replace custom CMOS gates with reconfigurable STT-based LUTs during design implementation such that the functionality of STT-based components and therefore the entire design cannot be determined in any manageable time, rendering any design reverse engineering attack ineffective. Our study conducted on a large number of standard circuit benchmarks concludes significant resiliency of hybrid STT-CMOS circuits against various types of attacks. Furthermore, the selection algorithms on average have a small impact of less than 3%, 8%, and 3% on design parametric constraints including performance, power and area, respectively.