VLSI Specification, Verification and Synthesis
VLSI Specification, Verification and Synthesis
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VLSI规范、验证和综合
DOI：
10.1007/978-1-4613-2007-4
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发表时间：
2013
期刊：
影响因子：
--
通讯作者：
P. Subrahmanyam
中科院分区：
文献类型：
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作者：
G. Birtwistle;P. Subrahmanyam
众所周知，要完成这本书，您可能不需要一次立即获得它。一天中的活动可能会让您感到很无聊。如果您尝试强迫阅读，则可能更喜欢做其他娱乐活动。但是，我们希望您拥有这本书的概念之一是，它不会让您感到无聊。除非您不喜欢这本书，否则在阅读时会感到无聊。 VLSI规范验证和合成确实提供了每个人想要的东西。
As known, to finish this book, you may not need to get it at once in a day. Doing the activities along the day may make you feel so bored. If you try to force reading, you may prefer to do other entertaining activities. But, one of concepts we want you to have this book is that it will not make you feel bored. Feeling bored when reading will be only unless you don't like the book. vlsi specification verification and synthesis really offers what everybody wants.