Gate-Recessed Normally OFF GaN MOSHEMT With High-Temperature Oxidation/Wet Etching Using LPCVD Si3N4 as the Mask
Gate-Recessed Normally OFF GaN MOSHEMT With High-Temperature Oxidation/Wet Etching Using LPCVD Si3N4 as the Mask
复制标题
使用 LPCVD Si3N4 作为掩模进行高温氧化/湿法刻蚀的栅极凹进式常关 GaN MOSHEMT
DOI：
10.1109/ted.2018.2812215
复制
发表时间：
2018-05-01
影响因子：
3.1
通讯作者：
Wang, Maojun
中科院分区：
文献类型：
--
作者：
Gao, Jingnan;Jin, Yufeng;Wang, Maojun
A gate-recessed normally OFF GaN metal-oxide-semiconductor high-electron-mobility transistor on silicon substrate has been fabricated using a self-terminated, plasma-free oxidation and wet etching process with pre-recess low-pressure chemical vapor deposition (LPCVD) Si3N4 passivation layer. The LPCVD Si3N4 serves the dual role of gate-recess mask and passivation layer. Unlike conventional oxidation etching process using Si3N4 as post gate-recess passivation, the gate channel region was prevented from additional plasma bombardment during the gate window re-opening. As a result, a high-effective channel mobility of 843 cm(2)/V . s, and low-channel resistance of 0.89 Omega . mm are achieved for a normally OFF channel with L-G = 1.5 mu m. For 3 mu m L-GD, the fabricated devices exhibit a threshold voltage (Vth) of 1.35 V, a maximum drain current of similar to 500 mA/mm, a high ON/OFF current ratio of similar to 1010, and 560-V OFF-state breakdown voltage together with a low-forward gate leakage current of similar to 10-7 mA/mm up to 10 V. A high Baliga's figure of merit of 1.26 GW/cm(2) is achieved in devices with 10-mu m gate-drain distance.
